WORKING X3T9.2 DRAFT 948D Revision 0 September-1-93 Information technology - AT Attachment Interface with Extensions (ATA-2) This is a working draft of a proposed American National Standard of Accredited Standards Committee X3. As such this is not a completed standard, has not yet received any form of approval within X3, X3T9 or X3T9.2. It is undergoing significant changes and is subject to additional changes in all areas. Use of the information contained herein is at your own risk. Permission is granted to members of X3, its technical committees, and their associated task groups to reproduce this document for the purposes of X3 standardization activities without further permission, provided this notice is included. All other rights are reserved. Any commercial or for-profit use is strictly prohibited. ASC X3T9.2 Technical Editor: Stephen G. Finch Silicon Systems, Inc. 14351 Myford Road Tustin, CA 92680-7022 USA Telephone: 714-573-6808 Facsimile: 714-573-6914 Email: 5723283@mcimail.com Reference number ISO/IEC ***** : 199x ANSI X3.221 - 199x Printed September, 1, 1993 9:16AM POINTS OF CONTACT: X3T9.2 Chair X3T9.2 Vice-Chair John B. Lohmeyer I. Dal Allan NCR Corporation ENDL 1635 Aeroplaza Drive 14426 Black Walnut Court Colorado Springs, CO 80916 Saratoga, CA 95070 Tel: (719) 596-5795 x362 Tel: (408) 867-6630 Fax: (719) 597-8225 Fax: (408) 867-2115 Email: john.lohmeyer@ftcollinsco.ncr.com Email: 2501752@mcimail.com X3 Secretariat Lynn Barra Administrator Standards Processing X3 Secretariat Telephone: 202-626-5738 1250 Eye Street, NW Suite 200 Facsimile: 202-638-4922 Washington, DC 20005 SCSI Reflector Internet address for subscription to the SCSI reflector: scsiadm@wichitaks.ncr.com Internet address for distribution via SCSI reflector: scsi@wichitaks.ncr.com SCSI Bulletin Board 719-574-0424 Document Distribution Global Engineering Telephone: 303-792-2181 or 15 Inverness Way East 800-854-7179 Englewood, CO 80112-5704 Facsimile: 303-792-2192 ABSTRACT The draft standard for AT Attachment Interface For Disk Drives has been completed, but as the popularity of the interface has increased, its application area has grown outside the originally intended purpose. This draft proposed standard is based upon the AT Attachment Interface For Disk Drives. This document is a stand alone document, separate from that document. The ATA Extensions (ATA-2) standard is intended to broaden the scope and application area and take advantage of the huge installed BIOS (Basic Input/Output System) base, and software. The proposed ATA-2 standard shall maintain a high degree of compatibility with the AT Attachment while providing documentation for new capabilities. This proposed standard is not intended to require changes to presently installed devices or existing software. It is intended that this proposed standard would be used to provide additional capabilities. The proposed ATA-2 standard involves evolutionary expansion of the draft AT Attachment standard to provide additional capabilities. The nature of the proposed project is to insure that the AT Attachment has an upward, highly compatible growth path. This will insure that current investments in AT Attachment are provided with more stability in the face of technological developments. It is likely that any isolated negative impacts would occur in any case through non-standard evolution or revolution. PATENT STATEMENT The developers of this standard have requested that holder's of patents that may be required for the implementation of the standard, disclose such patents to the publisher. However neither the developers nor the publisher have undertaken a patent search in order to identify which if any patents may apply to this standard. No position is taken with respect to the validity of any claim or any patent rights that may have been disclosed. Details of submitted statements may be obtained from the publisher concerning any statement of patents and willingness to grant a license under these rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license. DOCUMENT STATUS Revision 0 - initial document. Created from X3T9.2/791D Revision 4a, the proposed AT Attachment Interface For Disk Drives standard, and proposed changes contained in X3T9.2/93-009r0, with exception of those changes contained in X3T9.2/93-009r0 regarding Format Track Logical Block. It is the intent of the editor that any changes that may be made to X3T9.2/791D by X3T9.2 be implemented in this document as well. In addition, the editor has taken the liberty to re-arrange the contents of the document and make improvements as deemed necessary, understanding that the entire document is subject to review and change. Contents Page Foreword 10 Introduction 11 1. Scope 12 2. Normative references 12 3. Definitions, abbreviations and conventions 12 3.1. Definitions and Abbreviations 12 3.1.1. ATA (AT attachment) 12 3.1.2. AWG 12 3.1.3. CHS (Cylinder-head-sector) 12 3.1.4. Data block 12 3.1.5. DMA (Direct memory access) 13 3.1.6. LBA (Logical block address) 13 3.1.7. Optional 13 3.1.8. PIO (Programmed input/output) 13 3.1.9. Reserved 13 3.1.10. Vendor unique 13 3.2. Conventions 13 3.2.1. Keywords 13 3.2.2. Bit conventions 14 3.2.3. Numbering 14 3.2.4. Signal conventions 14 4. Interface Physical and Electrical Requirements 14 4.1. Configuration 15 4.2. DC cable and connector 15 4.2.1. 4-pin power 16 4.2.2. 3-pin power 16 4.3. Device grounding 17 4.4. I/O connector 17 4.5. I/O cable 17 4.6. AC Electrical Requirements 18 5. Interface Signal Assignments and Descriptions 18 5.1. Signal summary 18 5.2. Signal descriptions 20 5.2.1. CS0- (Chip select 0) 20 5.2.2. CS1- (CHIP SELECT 1) 20 5.2.3. DA2, DA1, and DA0 (Device address bus) 20 5.2.4. DASP- (Drive active, SLAVE (drive 1) present) 20 5.2.5. DD0-DD15 (Drive data bus) 21 5.2.6. DIOR- (Drive I/O read) 21 5.2.7. DIOW- (Drive I/O write) 21 5.2.8. DMACK- (DMA acknowledge) (Optional) 21 5.2.9. DMARQ (DMA request) (Optional) 21 5.2.10. INTRQ (Drive interrupt) 21 5.2.11. IOCS16- (Drive 16-bit I/O) 22 5.2.12. IORDY (I/O channel ready) (Optional) 22 5.2.13. PDIAG- (Passed diagnostics) 22 5.2.14. RESET- (Drive reset) 23 5.2.15. SPSYNC:CSEL (Spindle synchronization/cable select) (Optional) 23 5.2.15.1. SPSYNC (Spindle synchronization) (Optional) 23 5.2.15.2. CSEL (Cable select) (Optional) 24 6. Interface Register Definitions and Descriptions 24 6.1. General 24 6.2. Addressing considerations 24 6.2.1. Environment 24 6.3. I/O register descriptions 26 6.3.1. Alternate Status register 27 6.3.2. Command register 27 6.3.3. Cylinder High register 27 6.3.4. Cylinder Low register 27 6.3.5. Data register 27 6.3.6. Device Control register 28 6.3.7. Drive Address register 28 6.3.8. Drive/Head register 29 6.3.9. Error register 29 6.3.10. Features register 30 6.3.11. Sector Count register 30 6.3.12. Sector Number register 30 6.3.13. Status register 31 7. General Operational Requirements 32 7.1. Reset response 32 7.2. Translate mode 32 7.3. Power conditions 33 7.4. Error posting 34 8. Command Descriptions 35 8.1. ACKNOWLEDGE MEDIA CHANGE (removable) 37 8.2. BOOT - POST-BOOT (removable) 37 8.3. BOOT - PRE-BOOT (removable) 37 8.4. CHECK POWER MODE 37 8.5. DOOR LOCK (removable) 37 8.6. DOOR UNLOCK (removable) 37 8.7. Download Microcode 37 8.8. EXECUTE DRIVE DIAGNOSTIC 39 8.9. FORMAT TRACK 40 8.10. IDENTIFY DRIVE 41 8.10.1. Word 1: Number of cylinders 42 8.10.2. Word 3: Number of heads 42 8.10.3. Word 4: Number of unformatted bytes per track 43 8.10.4. Word 5: Number of unformatted bytes per sector 43 8.10.5. Word 6: Number of sectors per track 43 8.10.6. Word 10-19: Serial Number 43 8.10.7. Word 20: Buffer Type 43 8.10.8. Word 22: ECC bytes available on READ/WRITE LONG commands 43 8.10.9. Word 23-26: Firmware revision 43 8.10.10. Word 27-46: Model number 43 8.10.11. Word 49 43 8.10.12. IORDY Support 43 8.10.13. IORDY Can Be Disabled 43 8.10.14. Word 51: PIO data transfer cycle timing mode 44 8.10.15. Word 52: DMA data transfer cycle timing mode 44 8.10.16. Word 53: Field Validity 44 8.10.17. Word 54: Number of current cylinders 44 8.10.18. Word 55: Number of current heads 44 8.10.19. Word 56: Number of current sectors per track 44 8.10.20. Word 57-58: Current capacity in sectors 44 8.10.21. Word 59: Multiple sector setting 44 8.10.22. Word 60-61: Total number of user addressable sectors 44 8.10.23. Word 62: Single word DMA transfer 45 8.10.24. Word 63: Multiword DMA transfer 45 8.10.25. Word 64: Flow Control PIO Transfer Modes Supported 45 8.10.26. Word 65: Minimum Multiword DMA Transfer Cycle Time Per Word 45 8.10.27. Word 66: Manufacturer's Recommended Multiword DMA Transfer Cycle Time 45 8.10.28. Word 67: Minimum PIO Transfer Cycle Time Without Flow Control 46 8.10.29. Word 68: Minimum PIO Transfer Cycle Time With IORDY Flow Control 46 8.10.30. Words 69 and 70 46 8.11. IDLE 47 8.12. IDLE IMMEDIATE 47 8.13. INITIALIZE DRIVE PARAMETERS 47 8.14. NOP 48 8.15. READ BUFFER 48 8.16. READ DMA 48 8.17. READ LONG 48 8.18. READ MULTIPLE command 49 8.19. READ SECTOR(S) 50 8.20. READ VERIFY SECTOR(S) 50 8.21. RECALIBRATE 50 8.22. SEEK 51 8.23. SET FEATURES 51 8.24. SET MULTIPLE MODE 52 8.25. SLEEP 52 8.26. STANDBY 53 8.27. STANDBY IMMEDIATE 53 8.28. WRITE BUFFER 53 8.29. WRITE DMA 53 8.30. WRITE LONG 54 8.31. WRITE MULTIPLE command 54 8.32. WRITE SAME 55 8.33. WRITE SECTOR(S) 55 8.34. WRITE VERIFY 55 9. Protocol 56 9.1. PIO data in commands 56 9.1.1. PIO read command 56 9.1.2. PIO Read aborted command 56 9.2. PIO data out commands 57 9.2.1. PIO write command 57 9.2.2. PIO write aborted command 57 9.3. Non-data commands 58 9.4. Miscellaneous commands 58 9.5. DMA data transfer commands (optional) 59 9.5.1. Normal DMA transfer 59 9.5.2. Aborted DMA transfer 59 9.5.3. Aborted DMA Command 59 10. Timing 60 10.1. Deskewing 60 10.2. Symbols 60 10.3. Terms 60 10.4. Data Transfers 61 10.5. Power on and hard reset 64 Annex A. Diagnostic and reset considerations 65 A.1. Power on and hardware resets 65 A.1.1. Power on and hardware resets - one drive 65 A.1.2. Power on and hardware resets - two drives 65 A.1.2.1. Drive 1 65 A.1.2.2. Drive 0 66 A.2. Software reset 66 A.2.1. Software reset - one drive 66 A.2.2. Software reset - two drives 66 A.2.2.1. Drive 1 66 A.2.2.2. Drive 0 66 A.3. Diagnostic Command Execution 67 A.3.1. Diagnostic command execution - one drive (passed) 67 A.3.2. Diagnostic command - two drives (passed) 67 A.3.2.1. Drive 1 67 A.3.2.2. Drive 0 67 A.3.3. Diagnostic command execution - one drive (failed) 67 A.3.4. Diagnostic command execution - two drives (drive 1 failed) 67 A.3.4.1. Drive 1 67 A.3.4.2. Drive 0 68 Annex B. Diagnostic and reset considerations 69 B.1. Power on and hardware reset (RESET-) 69 B.2. Software reset 69 B.3. Drive diagnostic command 69 B.4. Truth table 69 B.5. Power on or hardware reset algorithm 69 B.6 Software Reset Algorithm 71 B.7. Diagnostic Command Algorithm 72 Annex C. 44-Pin Small Form Factor Connector 74 C.1. 44-pin signal assignments 74 Annex D. 68-Pin Small Form Factor Connector 76 D.1. Overview 76 D.2. Signals 76 D.4. Signal Descriptions 77 D.4.1. CD1- (Card Detect 1) 78 D.4.2. CD2- (Card Detect 2) 78 D.4.3. CS1- (Drive chip Select 1) 78 D.4.4. DMACK- (DMA Acknowledge) 78 D.4.5. DMARQ (DMA Request) 78 D.4.6. IORDY (I/O Channel Ready) 78 D.4.7. M/S- (Master/Slave) 78 D.4.8. SELATA- (Select 68-pin ATA) 78 D.5. Removability Considerations 79 D.5.1. Device Recommendations 79 D.5.2. Host Recommendations 79 Annex E. ATA Command Set Summary 80 Annex F. IBM PC AT(tm) Bus Addresses 83 Figures Page Figure 1 - ATA Interface Cabling Diagram 15 Figure 2 - 40-Pin Connector ounting 17 Figure 3 - Cable Select 24 Figure 4 - Format Track Data Field Format 40 Figure 5 - PIO Data Transfer to/from Drive 61 Figure 6 - IORDY Timing Requirements 62 Figure 7 - Single Word DMA Data Transfer 62 Figure 8 - Multiword DMA Data Transfer 63 Figure 9 - Reset Sequence 64 Tables Page Table 1 - DC Interface Using 4 Pin Power Connector 16 Table 2 - DC Interface Using 3 Pin Power Connector 16 Table 3 - AC Electrical Requirements 18 Table 4 - Interface Signal Names and Pin Assignments 19 Table 5 - Interface signals description 20 Table 6 - I/O Port Functions and Selection Addresses 26 Table 7 - Power Conditions 33 Table 8 - Register Usage 34 Table 9 - Command Codes and Parameters (Part 1 of 2) 35 Table 9 - Command Codes and Parameters (Part 2 of 2) 36 Table 10 - Features register Values for Download Microcode 38 Table 11 - Diagnostic Codes 39 Table 12 - Identify Drive Information (Part 1 of 2) 41 Table 12 - Identify Drive Information (Part 2 of 2) 42 Table 13 - Automatic Timeout Periods 47 Table 14 - Set Features register Definitions 51 Table 15 - Reset Error Register Values 69 Table 16 - Signal Assignments for 44-Pin ATA 75 Table 17 - Signal Assignments for 68-Pin ATA 77 Table 18 - Command Matrix 80 Table 19 - Commands Sorted By Command Value (Part 1 of 2) 81 Table 19 - Commands Sorted By Command Value (Part 2 of 2) 82 Foreword This standard will replace X3T9.2/791D, the proposed AT Attachment Interface for Disk Drives standard (the standard will be released as X3.221 once approved). This standard encompasses the following: Clause 1 describes the scope. Clause 2 lists the normative references. Clause 3 provides definitions, abbreviations and conventions used within this document. Clause 4 contains the electrical and mechanical characteristics; covering the interface cabling requirements of the DC, data cables and connectors. Clause 5 contains the signal descriptions of the AT Attachment Interface. Clause 6 contains descriptions of the registers of the AT Attachment Interface. Clause 7 describes the general operating requirements of the AT Attachment Interface. Clause 8 contains descriptions of the commands of the AT Attachment Interface. Clause 9 contains an overview of the protocol of the AT Attachment Interface. Clause 10 contains the interface timing diagrams. Annex A is informative. Annex B is informative. Annex C is informative. Annex D is informative. Annex E is informative. Introduction When the first IBM PC(tm) (Personal Computer) was introduced, there was no hard disk storage capability. Successive generations of product resulted in the inclusion of a hard disk as the primary storage device. When the PC AT(tm) was developed, a hard disk was the key to system performance, and the controller interface became a de facto industry interface for the inclusion of hard disks in PC ATs. The price of desktop systems has declined rapidly because of the degree of integration which reduced the number of components and interconnects. A natural outgrowth of this integration was the inclusion of controller functionality into the hard disk. In October 1988 a number of peripheral suppliers formed the Common Access Method Committee to encourage an industry-wide effort to adopt a common software interface to dispatch input/output requests to SCSI peripherals. Although this was the primary objective, a secondary goal was to specify what was known as the AT Attachment interface. The AT Attachment Interface For Disk Drives standard fulfilled that requirement. As personal computer type systems continued to evolve, there was a need to extend the capabilities of the interface. The lap-top and small computer systems needed to modify the mechanical aspects of the interface. High performance systems needed to have enhanced transfer rates. The wide spread acceptance of the AT Attachment Interface made it desirable to support additional device types such as removable disk storage, CD-ROM and tape units. In addition, there were a number of issues in the AT Attachment standard that needed to be addressed. 1. Scope This standard replaces the proposed AT Attachment Interface for Disk Drives standard, X3T9.2/791D (the standard will be released as X3.221 once approved). This standard extends the AT Attachment Interface with the addition of new commands, and defining improved interface transfer rates. In addition, general improvements have been made in content for completeness and to improve clarity. This standard defines the AT Attachment Interface. This standard defines an integrated bus which interfaces between disk drives and/or other types of devices and host processors. It provides a common point of attachment for systems manufacturers, system integrators, and suppliers of intelligent peripherals. The application environment for the AT Attachment Interface is any computer which uses the 40-pin ATA interface. The PC AT Bus(tm) is a widely used and implemented interface for which a variety of peripherals have been manufactured. As a means of reducing size and cost, a class of products has emerged which embed the controller functionality in the drive. Because of their compatibility with existing AT hardware and software this interface quickly became a de facto industry standard. While the AT Attachment Interface has its roots in the PC AT Bus(tm), its use has extended to many other systems. 2. Normative references The AT Attachment Interface for Disk Drives, X3T9.2/93-791D. [Editor's note: should use standard number, once it is approved.] 3. Definitions, abbreviations and conventions 3.1. Definitions and Abbreviations For the purposes of this International Standard, the following definitions apply. 3.1.1. ATA (AT attachment) ATA defines a register set, a 40-pin connector and the associated signals on the connector. 3.1.2. AWG American Wire Gauge. 3.1.3. CHS (Cylinder-head-sector) This term defines the addressing mode of the drive as being by physical sector address. The physical sector address is made up of three fields: the SECTOR NUMBER, the head number and the cylinder number. Sectors are numbered from 1 to a device specific maximum value which can not exceed 255. Heads are numbered from 0 to a device specific maximum value which can not exceed 15. Cylinders are numbered from 0 to a device specific maximum value which can not exceed 65,535. Typically, sequential access to the media is accomplished by treating the sector number as the least significant portion, the head number as the mid portion, and the cylinder number as the most significant portion of the CHS address. 3.1.4. Data block This term describes a unit of data words transferred using PIO data transfer. A data block is transferred between the host and the device as a complete unit. A data block is a set of 256 words (512 bytes), except for data blocks of a READ MULTIPLE or WRITE MULTIPLE command. In these cases, the size of the data block may be changed by the SET MULTIPLE MODE command. 3.1.5. DMA (Direct memory access) A means of data transfer between peripheral and host memory without processor intervention. 3.1.6. LBA (Logical block address) This term defines the addressing mode of the drive as being by the linear mapping of sectors from 0 to a device specific maximum LBA number. The maximum LBA number can not exceed 268 435 455. 3.1.7. Optional This term describes features which are not required by the standard. However, if any feature defined by the standard is implemented, it shall be done in the way defined by the standard. Describing a feature as optional in the text is done to assist the reader. 3.1.8. PIO (Programmed input/output) A means of accessing device registers. PIO is also used to describe one form of data transfers. PIO data transfers are performed by the host processor utilizing PIO register accesses to the Data register. 3.1.9. Reserved Where this term is used for bits, bytes and fields that are set aside for future standardization, and shall be zero. 3.1.10. Vendor unique This term is used to describe bits, bytes, fields, code values and features which are reserved for vendor unique purposes. These bits, bytes, fields, code values and features not described in this standard, and may be used in a way that varies between vendors. 3.2. Conventions If there is a conflict between text and tables, the table shall be accepted as being correct. 3.2.1. Keywords Lower case is used for words having the normal English meaning. Certain words and terms used in this International Standard have a specific meaning beyond the normal English meaning. These words and terms are defined either in clause 3 or in the text where they first appear. The names of abbreviations, commands, fields, and acronyms used as signal names are in all uppercase (e.g., IDENTIFY DRIVE). Fields containing only one bit are usually referred to as the "name" bit instead of the "name" field. (See Clause 3.3.2 for the naming convention used for naming bits.) Names of device registers begin with a capital letter (e.g., Cylinder Low register). 3.2.2. Bit conventions Bit names are shown in all upper case letters except where a lower case n precedes a bit name. If there is no preceding n, then when BIT=1 the meaning of the bit is true, and when BIT=0 the meaning of the bit is false. If there is a preceding n, then when nBIT=0 the meaning of the bit is true and when nBIT=1 the meaning of the bit is false. 3.2.3. Numbering Numbers that are not immediately followed by a lower-case "b" or "h" are decimal values. Numbers that are immediately followed by a lower-case "b" (e.g., 01b) are binary values. Numbers that are immediately followed by a lower-case "h" (e.g., 3ah) are hexadecimal values. 3.2.4. Signal conventions Signal names are shown in all upper case letters. All signals are TTL compatible unless otherwise noted. All TTL signals are either a high active or low active signals. A dash character (-) at the end of a signal name indicates it is a low active signal. A low active signal is true when it is below ViL, and is false when it is above ViH. No dash at the end of a signal name indicates it is a high active signal. A high active signal is true when it is above ViH, and is false when it is below ViL. Asserted means that the signal is driven by an active circuit to its true state. Negated means that the signal is driven by an active circuit to its false state. Released means that the signal is not actively driven to any state. Some signals have bias circuitry that will pull the signal to either a true state or false state when no signal driver is actively asserting or negating the signal. These cases are noted under the description of the signal, and their released state is stated. Control signals that may be used for two mutually exclusive functions are identified with their two names separated by a colon e.g. SPSYNC:CSEL can be used for either the Spindle Sync (SPSYNC) or the Cable Select (CSEL) functions. 4. Interface Physical and Electrical Requirements [Editor's Note: The original ATA Interface existed solely as a 40 pin ribbon cable. Before the AT Attachment for Disk Drives standards began public review, an additional interface, the 44-pin Small Form Factor connector, was added in the form of an "informative annex". We are adding the 68 pin ATA connector (based on the PCMCIA connector), and the PCMCIA committee is referencing the ATA-1 document in their standard. In addition, we will be making changes to the ATA interface that may tighten the cable definition, driver and receiver definitions and add termination to the cable. We need to establish a defining/describing the "legal" tree of cabling/connecting versus tradeoffs such as speed, cable requirements, driver/receivers, and termination. HOW? I am open to suggestions.] 4.1. Configuration This standard defines the ATA interface as a bus containing a single host or host adapter and one or two devices. If two devices are connected to the bus, they are connected in a daisy chained configuration. One device is configured as Drive 0 (device 0) and the second drive as Drive 1 (device 1). If only one drive is connected to the ATA bus, it shall be addressed as Drive 0. Note: Within the industry, Drive 0 has also been referred to as the master, and Drive 1 as the slave. Note: Throughout this document, the terms Drive and Device are used interchangably, and have the same meaning. The designation of a device as Drive 0 or Drive 1 may be made in a number of ways: - a switch on the drive - a jumper plug on the drive - use of the Cable Select (CSEL) pin The order of placement of Drive 0 and Drive 1 on the ATA bus cable is not significant to the operation of the interface. +-----------+ | HOST | ATA interface | OR |-----------+---------------------+ | ADAPTER | | | +-----------+ +---------+ +---------+ | DRIVE 0 | | DRIVE 1 | +---------+ +---------+ Figure 1 - ATA Interface Cabling Diagram 4.2. DC cable and connector [Editor's Note: Does this standard specify the ATA bus (host connection and each of the devices) or does it specify the interface as seen at the devices connectors? I don't think we can adequately define the ATA interface by only specifying what is seen at the device connectors. If we do specify the ATA bus, I question the need for power connectors in this specification.] The drive receives DC power through a 4-pin or a low-power application 3-pin connector. 4.2.1. 4-pin power The pin assignments are shown in table 1. Recommended part numbers for the mating connector to 18 AWG cable are shown below, but equivalent parts may be used. Connector (4 pin) AMP 1-480424-0 or equivalent. Contacts (loose piece) AMP 60619-4 or equivalent. Contacts (strip) AMP 61117-4 or equivalent. [Editor's Note: Are these the device side connectors or the cable side connectors?] [Editor's Note: Does anyone else feel uneasy about specifying a manufacturer's part number? What if the manufacturer changes its specification for that part? As far as I know they are under no obligation to tell us. I know the history, keep it simple and get the ATA specification out, but does this approach apply to ATA-2 as well?] +========================-============+ | Power line designation | Pin number | |------------------------+------------| | +12V | 1-01 | | +12V Return | 1-02 | | +5V Return | 1-03 | | +5V | 1-04 | +=====================================+ Table 1 - DC Interface Using 4 Pin Power Connector [Editor's Note: How do we specify the pin one orientation?] 4.2.2. 3-pin power The pin assignments are shown in table 2. Recommended part numbers for the mating connector to 18 AWG cable are shown below, but equivalent parts may be used. Connector (3 pin) Molex 5484 39-27-0032 or equivalent. [Editor's Note: Is this the device side connectors or the cable side connectors?] +========================-============+ | Power line designation | Pin number | |------------------------+------------| | +5V | +3,3V | 1-01 | | +12V | +5V | 1-02 | | Ground | Ground | 1-03 | +=====================================+ Table 2 - DC Interface Using 3 Pin Power Connector [Editor's Note: How do we specify the pin one orientation?] A drive designed for 3,3V applications may be plugged into a receptacle designed to accept a drive designed for 5V applications, with 12V lines for additional power. It is not required that the drive operate, but it is recommended that precautions be taken to prevent damage to the drive. A drive designed for 5V applications may be plugged into a receptacle designed to accept a drive designed for 3,3V applications, with 5V lines for additional power. It is not anticipated that damage could occur to the drive, but it is likely to fail in an undetermined manner. 4.3. Device grounding System ground may be connected to a "quick-connect" terminal equivalent to: Drive connector terminal AMP 61664-1 or equivalent. Cable connector terminal AMP 62137-2 or equivalent. Provision for tying the DC logic ground and the chassis ground together or for separating these two ground planes is vendor specific. 4.4. I/O connector The I/O connector is a 40-pin connector as shown in figure 4, with pin assignments as shown in table 4. The connector should be keyed to prevent the possibility of installing it upside down. A key is provided by the removal of pin 20. The corresponding pin on the cable connector should be plugged. The pin locations are governed by the cable plug, not the receptacle. The way in which the receptacle is mounted on the printed circuit board affects the pin positions, and pin 1 should remain in the same relative position. This means the pin numbers of the receptacle may not reflect the conductor number of the plug. The header receptacle is not polarized, and all the signals are relative to pin 20, which is keyed. By using the plug positions as primary, a straight cable can connect drives. As shown in figure 4, conductor 1 on pin 1 of the plug has to be in the same relative position no matter what the receptacle numbering looks like. If receptacle numbering was followed, the cable would have to twist 180 degrees between a drive with top-mounted receptacles, and a drive with bottom-mounted receptacles. +-----------------------+ | 1| |40 20 2| ======= Circuit board ======= ==-==== Circuit board ====-== | 1| |40 20 2| +-----------------------+ Figure 2 - 40-Pin Connector Mounting Recommended part numbers for the mating connector are shown below, but equivalent parts may be used. Connector (40 pin) 3M 3417-7000 or equivalent. Strain relief 3M 3448-2040 or equivalent. 4.5. I/O cable The cable specifications affect system integrity and the maximum length that can be supported in any application. Flat cable (stranded 28 AWG) 3M 3365-40 or equivalent. Flat cable (stranded 28 AWG) 3M 3517-40 (shielded) or equivalent. Cable length of 0,46m (18 inches). This distance may be exceeded in circumstances where the characteristics of both ends of the cable can be controlled. Cable capacitance shall not exceed 35 pF. 4.6. AC Electrical Requirements +-------------------------------------------+------+--------+ | Description | Min | Max | +--------+-------------------------------------------+------+--------+ | IoL | Driver sink current for 5V operation | 12mA | | | IoL | Driver sink current for 3,3V operation | 8mA | | | IoH | Driver source current | | -400uA | | Vih | Voltage Input High | 2,0 V| | | Vil | Voltage Input Low | | 0,8 V | | Voh | Voltage Output High (Ioh = -400 u A) | 2,4 V| | | Vol | Voltage Output Low (5V, Iol = 12ma) | | 0,5 V | | Vol | Voltage Output Low (3,3V, Iol = 8ma) | | 0,5 V | | Cin | Input Capacitance (of Device) | | 25 pf | | Cout | Output Capacitance (of Device) | | 25 pf | | tRISE | Rise time for any signal on AT interface | 5ns | | | tFALL | Rise time for any signal on AT interface | 5ns | | +--------+-------------------------------------------+------+--------+ Table 3 - AC Electrical Requirements [Editor's note: IoH value at 400 uA is insufficient at least in the case of DMARQ which is typically pulled low by a 5.6k resistor.] [Editor's note: IoL value is a minimum number. Do we need a maximum number? In an environment where there is no cable, are the minimum numbers too high?] 5. Interface Signal Assignments and Descriptions 5.1. Signal summary The physical interface consists of TTL compatible receivers and drivers communicating through a 40-conductor flat ribbon non-shielded cable using an asynchronous interface protocol. The pin numbers and signal names are shown in table 4. Reserved signals shall be left unconnected. Table 5 is contains an alphabetically listing by pin acronym. +========================+=============+====+===========+ | Description | Source |Pin | Acronym | +------------------------+-------------+----+-----------+ | Reset | Host | 1 | RESET- | | | n/a | 2 | Ground | | Data bus bit 7 | Host/Device | 3 | DD7 | | Data bus bit 8 | Host/Device | 4 | DD8 | | Data bus bit 6 | Host/Device | 5 | DD6 | | Data bus bit 9 | Host/Device | 6 | DD9 | | Data bus bit 5 | Host/Device | 7 | DD5 | | Data bus bit 10 | Host/Device | 8 | DD10 | | Data bus bit 4 | Host/Device | 9 | DD4 | | Data bus bit 11 | Host/Device | 10 | DD11 | | Data bus bit 3 | Host/Device | 11 | DD3 | | Data bus bit 12 | Host/Device | 12 | DD12 | | Data bus bit 2 | Host/Device | 13 | DD2 | | Data bus bit 13 | Host/Device | 14 | DD13 | | Data bus bit 1 | Host/Device | 15 | DD1 | | Data bus bit 14 | Host/Device | 16 | DD14 | | Data bus bit 0 | Host/Device | 17 | DD0 | | Data bus bit 15 | Host/Device | 18 | DD15 | | Ground | n/a | 19 | Ground | | (keypin) | n/a | 20 | Reserved | | DMA Request | Device | 21 | DMARQ | | Ground | n/a | 22 | Ground | | I/O Write | Host | 23 | DIOW- | | Ground | n/a | 24 | Ground | | I/O Read | Host | 25 | DIOR- | | Ground | n/a | 26 | Ground | | I/O Ready | Device | 27 | IORDY | | Spindle Sync or | (note 1) | 28 | SPSYNC: | | Cable Select | | | CSEL | | DMA Acknowledge | Host | 29 | DMACK- | | Ground | n/a | 30 | Ground | | Interrupt Request | Device | 31 | INTRQ | | 16 Bit I/O | Device | 32 | IOCS16- | | Device Address Bit 1 | Host | 33 | DA1 | | PASSED DIAGNOSTICS | (note 1) | 34 | PDIAG- | | Device Address Bit 0 | Host | 35 | DAO | | Device Address Bit 2 | Host | 36 | DA2 | | Chip Select 0 | Host | 37 | CS0- | | Chip Select 1 | Host | 38 | CS1- | | Drive Active or | (note 1) | 39 | DASP- | | Slave(Drive 1) Present| | | | | Ground | n/a | 40 | Ground | +------------------------+-------------+----+-----------+ | Note 1: See signal descriptions for information | | on source of these signals | +=======================================================+ Table 4 - Interface Signal Names and Pin Assignments +=========+=========+ +=========+=========+ | Signal | Pin | | Signal | Pin | +---------+---------+ +---------+---------+ | CS0- | 37 | | DD11 | 10 | | CS1- | 38 | | DD12 | 12 | | DA0 | 35 | | DD13 | 14 | | DA1 | 33 | | DD14 | 16 | | DA2 | 36 | | DD15 | 18 | | DASP- | 39 | | DIOR- | 25 | | DD0 | 17 | | DIOW- | 23 | | DD1 | 15 | | DMACK- | 29 | | DD2 | 13 | | DMARQ | 21 | | DD3 | 11 | | INTRQ | 31 | | DD4 | 9 | | IOCS16- | 32 | | DD5 | 7 | | IORDY | 27 | | DD6 | 5 | | PDIAG- | 34 | | DD7 | 3 | | RESET- | 1 | | DD8 | 4 | | SPSYNC: | 28 | | DD9 | 6 | | CSEL | 28 | | DD10 | 8 | | keypin | 20 | | DD11 | 10 | | ground | 2,19,22,| | | | | |24,26,30,| | | | | |40 +=========|=========| |=========|=========| Table 5 - Interface signals - Alphabetical Listing 5.2. Signal descriptions 5.2.1. CS0- (CHIP SELECT 0) This is the chip select signal from the host used to select the Command Block Registers. Note: This signal has also been known in the industry as CS1FX-. 5.2.2. CS1- (CHIP SELECT 1) This is the chip select signal from the host used to select the Control Block Registers. Note: This signal has also been known in the industry as CS3FX-. 5.2.3. DA2, DA1, and DA0 (DEVICE ADDRESS BUS) This is the 3-bit binary coded address asserted by the host to access a register or data port in the drive. 5.2.4. DASP- (DRIVE ACTIVE, SLAVE (DRIVE 1) PRESENT) This signal is not TTL compatible. This is a time-multiplexed signal which indicates that a drive is active, or that Drive 1 is present. This signal shall be an open collector output and each drive shall have a 10K ohm pull-up resistor. During power on initialization or after RESET- is negated, DASP- shall be deasserted by both Drive 0 and Drive 1 within 1 msec, and then Drive 1 shall assert DASP- within 400 msec to indicate that Drive 1 is present. Drive 0 shall allow up to 450 msec for Drive 1 to assert DASP-. If Drive 1 is not present, Drive 0 may assert DASP- to drive an activity LED. DASP- shall be negated following acceptance of the first valid command by Drive 1 or after 31 seconds, whichever comes first. Any time after negation of DASP-, either drive may assert DASP- to indicate that a drive is active. NOTE 1 Prior to the development of this standard, products were introduced which did not time multiplex DASP-. Some used two jumpers to indicate to Drive 0 whether Drive 1 was present. If such a drive is jumpered to indicate Drive 1 is present it should work successfully with a Drive 1 which complies with this standard. If installed as Drive 1, such a drive may or may not work successfully because it may not assert DASP- for a long enough period to be recognized. However, it would assert DASP-to indicate that the drive is active. 5.2.5. DD0-DD15 (Drive data bus) This is an 8- or 16-bit bi-directional data bus between the host and the drive. The lower 8 bits are used for 8-bit transfers e.g. registers, ECC bytes and, if the drive supports the Features register capability to enable 8-bit-only data transfers (see 9.22). 5.2.6. DIOR- (Drive I/O read) This is the Read strobe signal. The falling edge of DIOR- enables data from a register or the data port of the drive onto the host data bus, DD0-DD7 or DD0-DD15. The rising edge of DIOR- latches data at the host. 5.2.7. DIOW- (Drive I/O write) This is the Write strobe signal. The rising edge of DIOW- clocks data from the host data bus, DD0-DD7 or DD0-DD15, into a register or the data port of the drive. 5.2.8. DMACK- (DMA acknowledge) (Optional) This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. 5.2.9. DMARQ (DMA request) (Optional) This signal, used for DMA data transfers between host and drive, shall be asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK- i.e. the drive shall wait until the host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more data to transfer. When a DMA operation is enabled, IOCS16-, CS0- and CS1- shall not be asserted and transfers shall be 16-bits wide. NOTE 2 ATA products with DMA capability require a pull-down resistor on this signal to prevent spurious data transfers. This resistor may affect driver requirements for drives sharing this signal in systems with unbuffered ATA signals. 5.2.10. INTRQ (Drive interrupt) This signal is used to interrupt the host system. INTRQ is asserted only when the drive has a pending interrupt, the drive is selected, and the host has cleared nIEN in the Device Control register. If nIEN=1, or the drive is not selected, this output is in a high impedance state, regardless of the presence or absence of a pending interrupt. INTRQ shall be negated by: - assertion of RESET- or - the setting of SRST of the Device Control register, or - the host writing the Command register or - the host reading the Status register NOTE 3 Some drives may negate INTRQ on a PIO data transfer completion, except on a single sector read or on the last sector of a multi-sector read. On PIO transfers, INTRQ is asserted at the beginning of each data block to be transferred. A data block is typically a single sector, except when declared otherwise by use of the SET MULTIPLE MODE command. An exception occurs on FORMAT TRACK, WRITE SECTOR(S), WRITE BUFFER and WRITE LONG commands - INTRQ shall not be asserted at the beginning of the first data block to be transferred. On DMA transfers, INTRQ is asserted only once, after the command has completed. 5.2.11. IOCS16- (Drive 16-bit I/O) Except for DMA transfers, IOCS16- indicates to the host system that the 16-bit data port has been addressed and that the drive is prepared to send or receive a 16-bit data word. This shall be an open collector output. * When transferring in PIO mode, if IOCS16- is not asserted, transfers shall be 8-bit using DD0-7. * When transferring in PIO mode, if IOCS16- is asserted, transfers shall be 16-bit using DD0-15. * When transferring in DMA mode, the host shall use a 16-bit DMA channel and IOCS16- shall not be asserted. 5.2.12. IORDY (I/O channel ready) (Optional) This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the drive is not ready to respond to a data transfer request. When IORDY is not negated, IORDY shall be in a high impedance state. 5.2.13. PDIAG- (Passed diagnostics) This signal shall be asserted by Drive 1 to indicate to Drive 0 that it has completed diagnostics. A 10K ohm pull-up resistor shall be used on this signal by each drive. Following a power on reset, software reset or RESET-, Drive 1 shall negate PDIAG- within 1 msec (to indicate to Drive 0 that it is busy). Drive 1 shall then assert PDIAG- within 30 seconds to indicate that it is no longer busy, and is able to provide status. If Drive 1 is present, then Drive 0 shall wait for up to 31 seconds from power-on reset, software reset or RESET- for Drive 1 to assert PDIAG-. If Drive 1 fails to assert PDIAG-, Drive 0 shall set bit 7 to 1 in the Error register to indicate that Drive 1 failed. After the assertion of PDIAG-, Drive 1 may be unable to accept commands until it has finished its reset procedure and is Ready (DRDY=1). Following the receipt of a valid EXECUTE DRIVE DIAGNOSTIC command, Drive 1 shall negate PDIAG- within 1 msec to indicate to Drive 0 that it is busy and has not yet passed its drive diagnostics. Drive 1 shall then assert PDIAG- within 5 seconds to indicate that it is no longer busy, and is able to provide status. Drive 1 should clear BSY before asserting PDIAG-. If Drive 1 is present then Drive 0 shall wait for up to 6 seconds from the receipt of a valid EXECUTE DRIVE DIAGNOSTIC command for Drive 1 to assert PDIAG-. If Drive 1 fails to assert PDIAG-, Drive 0 shall set bit 7 to 1 in the Error register to indicate that Drive 1 failed. If DASP- was not asserted by Drive 1 during reset initialization, Drive 0 shall post its own status immediately after it completes diagnostics, and clear the Drive 1 Status register to 00h. Drive 0 may be unable to accept commands until it has finished its reset procedure and is Ready (DRDY=1). 5.2.14. RESET- (Drive reset) This signal from the host system shall be asserted for at least 25 usec after voltage levels have stabilized during power on and negated thereafter unless some event requires that the drive(s) be reset following power on. 5.2.15. SPSYNC:CSEL (Spindle synchronization/cable select) (Optional) This signal shall have a 10K ohm pull-up resistor. This is a dual purpose signal and either or both functions may be implemented. If both functions are implemented then they cannot be active concurrently: the choice as to which is active is made by a vendor-defined switch. All drives connected to the same cable should have the same function active at the same time. If SPSYNC and CSEL are mixed on the same cable, then drive behavior is undefined. Prior to the introduction of this standard, this signal was defined as DALE (Drive Address Latch Enable), and used for an address valid indication from the host system. If used, the host address and chip selects, DAO through DA2, CS0-, and CS1- were valid at the negation of this signal and remained valid while DALE was negated, therefore, the drive did not need to latch these signals with DALE. 5.2.15.1. SPSYNC (Spindle synchronization) (Optional) This signal may be either input or output to the drive depending on a vendor-defined switch. If a drive is set to Drive 0 the signal is output, and if a drive is set to slave the signal is input. There is no requirement that each drive implementation be plug-compatible to the extent that a multiple vendor drive subsystem be operable. Mix and match of different manufacturers drives is unlikely because rpm, sync fields, sync bytes etc. need to be virtually identical. However, if drives are designed to match the following recommendation, controllers can operate drives with a single implementation. There can only be one Drive 0 drive at a time in a configuration. The host or the drive designated as Drive 0 can generate SPSYNC at least once per rotation, but may be at a higher frequency. SPSYNC received by a drive is used as the synchronization signal to lock the spindles in step. The time to achieve synchronization varies, and is indicated by the drive setting DRDY i.e. if the drive is capable of spindle synchronization and if it is set to acquire synchronization from another SPSYNC source, but does not achieve synchronization following power on or a reset, it shall not set DRDY. Driver 0 or the host generates SPSYNC and transmits it. Drive 1 does not generate SPSYNC and is responsible to synchronize its index to SPSYNC. If a drive does not support synchronization, it shall ignore SPSYNC. In the event that a drive previously synchronized loses synchronization, but is otherwise operational, it does not clear DRDY. 5.2.15.2. CSEL (Cable select) (Optional) The drive is configured as either Drive 0 or Drive 1 depending upon the value of CSEL: * If CSEL is grounded then the drive address is 0 * If CSEL is open then the drive address is 1 Special cabling can be used by the system manufacturer to selectively ground CSEL e.g. CSEL of Drive 0 is connected to the CSEL conductor in the cable, and is grounded, thus allowing the drive to recognize itself as Drive 0. CSEL of Drive 1 is not connected to CSEL because the conductor is removed, thus the drive can recognize itself as Drive 1. +------ CSEL Conductor -------------------------+ | | Open |Ground | | +------+ +---------+ +---------+ | Host | | Drive 0 | | Drive 1 | +------+ +---------+ +---------+ +------ CSEL Conductor -------------------------+ | Open | |Ground | | +------+ +---------+ +---------+ | Host | | Drive 1 | | Drive 0 | +------+ +---------+ +---------+ Figure 3 - Cable Select 6. Interface Register Definitions and Descriptions 6.1. General 6.2. Addressing considerations In traditional controller operation, only the selected controller receives commands from the host following selection. In this standard, the register contents go to both drives (and their embedded controllers). The host discriminates between the two by using the DRV bit in the Drive/Head register. 6.2.1. Environment Data is transferred in parallel (16 bits) either to or from host memory to the drive's buffer under the direction of commands previously transferred from the host. The drive performs all of the operations necessary to properly write data to, or read data from, the media. Data read from the media is stored in the drive's buffer pending transfer to the host memory and data is transferred from the host memory to the drive's buffer to be written to the media. The drives using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two drives are daisy chained on the interface, commands are written in parallel to both drives, and for all except the Execute Diagnostics command, only the selected drive executes the command. On an Execute Diagnostics command addressed to Drive 0, both drives shall execute the command, and Drive 1 shall post its status to Drive 0 via PDIAG-. Drives are selected by the DRV bit in the Drive/Head register (see 7.2.8), and by a jumper or switch on the drive designating it as either a Drive 0 or as Drive 1. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected. When drives are daisy chained, one shall be set as Drive 0 and the other as Drive 1. When a single drive is attached to the interface it shall be set as Drive 0. Throughout this document, drive selection always refers to the state of the DRV bit, the position of the Drive 0/Drive 1 jumper or switch, or use of the CSEL pin. A drive can operate in either of two addressing modes, CHS or LBA, on a command by command basis. A drive which can support LBA mode indicates this in the Identify Drive Information. If the host selects LBA mode in the Drive/Head register, Sector Number register, Cylinder Low register, Cylinder High register and HS3-HS0 of the Drive/Head register contains the zero based-LBA. In LBA mode, the sectors on the drive are assumed to be linearly mapped with an Initial definition of: LBA 0 = (cylinder 0, head 0, sector 1). Irrespective of translate mode geometry set by the host, the LBA address of a given sector does not change: LBA = ((cylinder * heads_per_cylinder + heads) * sectors_per_track) + sector - 1 6.3. I/O register descriptions Communication to or from the drive is through an I/O Register that routes the input or output data to or from registers addressed by the signals from the host (CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-). The Command Block Registers are used for sending commands to the drive or posting status from the drive. The Control Block Registers are used for drive control and to post alternate status. Table 6 lists these registers and the addresses that select them. Logic conventions are: A = signal asserted N = signal negated x = does not matter which it is +===============================-==========================================+ | Addresses | Functions | |-------------------------------+------------------------------------------| | CS0- | CS1- | DA2 | DA1 | DA0 | READ (DIOR-) | WRITE (DIOW-) | |------+------+-----+-----+-----+------------------------------------------| | N | N | x | x | x | Data bus high imped | Not used | |------+------+-----+-----+-----+------------------------------------------| | | Control block registers | |-------------------------------+------------------------------------------| | N | A | 0 | x | x | Data bus high imped | Not used | | N | A | 1 | 0 | x | Data bus high imped | Not used | | N | A | 1 | 1 | 0 | ALTERNATE STATUS | DEVICE CONTROL | | N | A | 1 | 1 | 1 | DRIVE ADDRESS | Not used | |-------------------------------+------------------------------------------| | | Command block registers | |-------------------------------+------------------------------------------| | A | N | 0 | 0 | 0 | DATA | DATA | | A | N | 0 | 0 | 1 | ERROR REGISTER | FEATURES | | A | N | 0 | 1 | 0 | SECTOR COUNT | SECTOR COUNT | | A | N | 0 | 1 | 1 | SECTOR NUMBER | SECTOR NUMBER | | A | N | 0 | 1 | 1 | * LBA bits 0- 7 | * LBA bits 0- 7 | | A | N | 1 | 0 | 0 | CYLINDER LOW | CYLINDER LOW | | A | N | 1 | 0 | 0 | * LBA bits 8-15 | * LBA bits 8-15 | | A | N | 1 | 0 | 1 | CYLINDER HIGH | CYLINDER HIGH | | A | N | 1 | 0 | 1 | * LBA bits 16-23 | * LBA bits 16-23 | | A | N | 1 | 1 | 0 | DRIVE/HEAD | DRIVE/HEAD | | A | N | 1 | 1 | 0 | * LBA bits 24-27 | * LBA bits 24-27 | | A | N | 1 | 1 | 1 | STATUS | COMMAND | |-------------------------------+------------------------------------------| | A | A | x | x | x | Invalid address | Invalid address | |--------------------------------------------------------------------------| | * Mapping of registers in LBA mode | +==========================================================================+ Table 6 - I/O Port Functions and Selection Addresses 6.3.1. Alternate Status register This register contains the same information as the Status register in the command block. The only difference being that reading this register does not imply interrupt acknowledge or clear a pending interrupt. +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | BSY | DRDY | DWF | DSC | DRQ | CORR | IDX | ERR | +===============================================================+ See 7.2.13 for definitions of the bits in this register. 6.3.2. Command register This register contains the command code being sent to the drive. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in table 9. 6.3.3. Cylinder High register This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. The most significant bits of the cylinder address shall be loaded into the Cylinder High register. In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23. NOTE 4 Prior to the introduction of this standard, only the lower 2 bits of this register were valid, limiting cylinder address to 10 bits i.e. 1024 cylinders. 6.3.4. Cylinder Low register This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15. 6.3.5. Data register This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a FORMAT TRACK command. Data transfers may be either PIO or DMA. 6.3.6. Device Control register The bits in this register are as follows: +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | x | x | x | x | 1 | SRST | nIEN | 0 | +===============================================================+ * SRST is the host software reset bit. The drive is held reset when this bit is set. If two disk drives are daisy chained on the interface, this bit resets both simultaneously. Drive 1 is not required to execute the DASP-handshake procedure. * nIEN is the enable bit for the drive interrupt to the host. When nIEN=0, and the drive is selected, INTRQ shall be enabled through a tri-state buffer. When nIEN=1, or the drive is not selected, the INTRQ signal shall be in a high impedance state. 6.3.7. Drive Address register This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in this register are as follows: +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | HiZ | nWTG | nHS3 | nHS2 | nHS1 | nHS0 | nDS1 | nDS0 | +===============================================================+ * HiZ shall always be in a high impedance state. * nWTG is the Write Gate bit. When writing to the disk drive is in progress, nWTG=0. * nHS3 through nHS0 are the one's complement of the binary coded address of the currently selected head. For example, if nHS3 through nHS0 are 1100b, respectively, head 3 is selected. nHS3 is the most significant bit. * nDS1 is the drive select bit for drive 1. When drive 1 is selected and active, nDS1=0. * nDS0 is the drive select bit for drive 0. When drive 0 is selected and active, nDS0=0. NOTE 5 Care should be used when interpreting these bits, as they do not always represent the expected status of drive operations at the instant the status was put into this register. This is because of the use of caching, translate mode and the Drive 0/Drive 1 concept with each drive having its own embedded controller. 6.3.8. Drive/Head register This register contains the drive and head numbers. The contents bits 0 through 3 of this register define the number of heads minus 1, when executing an INITIALIZE DRIVE PARAMETERS command. +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | 1 | L | 1 | DRV | HS3 | HS2 | HS1 | HS0 | +===============================================================+ * L is the binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1, addressing is by LBA mode. * DRV is the binary encoded drive select number. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected. * If L=0, HS3 through HS0 contain the binary coded address of the head to be selected e.g. if HS3 through HS0 are 0011b, respectively, head 3 will be selected. HS3 is the most significant bit. At command completion, these bits are updated to reflect the currently selected head. * If L=1, HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits 24-27. 6.3.9. Error register This register contains status from the last command executed by the drive or a Diagnostic Code. At the completion of any command except EXECUTE DRIVE DIAGNOSTIC, the contents of this register are valid when ERR=1 in the Status register. Following a power on, a reset, or completion of an EXECUTE DRIVE DIAGNOSTIC command, this register contains a Diagnostic Code (see table 10). +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | BBK | UNC | MC | IDNF | MCR | ABRT | TK0NF | AMNF | +===============================================================+ * BBK (Bad Block Detected) indicates a bad block mark was detected in the requested sector's ID field. * UNC (Uncorrectable Data Error) indicates an uncorrectable data error has been encountered. * MC (Media Changed) indicates that the removable media has been changed i.e. there has been a change in the ability to access the media. * IDNF (ID Not Found) indicates the requested sector's ID field could not be found. * ABRT (Aborted Command) indicates the requested command has been aborted due to a drive status error (Not Ready, Write Fault, etc.) or because the command code is invalid. * MCR (Media Change Requested) indicates that the release latch on a removable media drive has been pressed. This means that the user wishes to remove the media and requires an action of some kind e.g. have software issue a Media Eject or DOOR UNLOCK command. * TK0NF (Track 0 Not Found) indicates track 0 has not been found during a RECALIBRATE command. * AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct ID field. 6.3.10. Features register This register is command specific and may be used to enable and disable features of the interface e.g. by the SET FEATURES Command to enable and disable caching. This register may be ignored by some drives. Some hosts, based on definitions prior to the completion of this standard, set values in this register to designate a recommended Write Precompensation Cylinder value. 6.3.11. Sector Count register This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the drive. If the value in this register is zero, a count of 256 sectors is specified. If this register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request. The contents of this register may be defined otherwise on some commands e.g. INITIALIZE DRIVE PARAMETERS, FORMAT TRACK or WRITE SAME commands. 6.3.12. Sector Number register This register contains the starting SECTOR NUMBER for any disk data access for the subsequent command. The SECTOR NUMBER may be from 1 to the maximum number of sectors per track. In LBA Mode this register contains Bits 0-7. At the end of the command, this register is updated to reflect the current LBA Bits 0-7. See the command descriptions for contents of the register at command completion (whether successful or unsuccessful). 6.3.13. Status register This register contains the drive status. The contents of this register are updated at the completion of each command. When BSY is cleared, the other bits in this register shall be valid within 400 nsec. If BSY=1, no other bits in this register are valid. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read. NOTE 6 If Drive 1 is not detected as being present, Drive 0 clears the Drive 1 Status register to 00h (indicating that the drive is Not Ready). +=======-=======-=======-=======-=======-=======-=======-=======+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |-------+-------+-------+-------+-------+-------+-------+-------| | BSY | DRDY | DWF | DSC | DRQ | CORR | IDX | ERR | +===============================================================+ NOTE 7 Prior to the definition of this standard, DRDY and DSC were unlatched real time signals. * BSY (Busy) is set whenever the drive has access to the Command Block Registers. The host should not access the Command Block Register when BSY=1. When BSY=1, a read of any Command Block Register shall return the contents of the Status register. This bit is set by the drive (which may be able to respond at times when the media cannot be accessed) under the following circumstances: a) within 400 nsec after the negation of RESET- or after SRST has been set in the Device Control register. Following acceptance of a reset it is recommended that BSY be set for no longer than 30 seconds by Drive 1 and no longer than 31 seconds by Drive 0. b) within 400 nsec of a host write of the Command register with a Read, READ LONG, READ BUFFER, SEEK, RECALIBRATE, INITIALIZE DRIVE PARAMETERS, Read Verify, IDENTIFY DRIVE, or EXECUTE DRIVE DIAGNOSTIC command. c) within 5 usecs following transfer of 512 bytes of data during execution of a Write, FORMAT TRACK, or WRITE BUFFER command, or 512 bytes of data and the appropriate number of ECC bytes during the execution of a WRITE LONG command. * DRDY (Drive Ready) indicates that the drive is capable of responding to a command. When there is an error, this bit is not changed until the Status register is read by the host, at which time the bit again indicates the current readiness of the drive. This bit shall be cleared at power on and remain cleared until the drive is ready to accept a command. * DWF (Drive Write Fault) indicates the current write fault status. When an error occurs, this bit shall not be changed until the Status register is read by the host, at which time the bit again indicates the current write fault status. * DSC (Drive Seek Complete) indicates that the drive heads are settled over a track. When an error occurs, this bit shall not be changed until the Status Register is read by the host, at which time the bit again indicates the current Seek Complete status. * DRQ (Data Request) indicates that the drive is ready to transfer a word or byte of data between the host and the drive. * CORR (Corrected Data) indicates that a correctable data error was encountered and the data has been corrected. This condition does not terminate a data transfer. * IDX (Index) is set once per disk revolution. * ERR (Error) indicates that an error occurred during execution of the previous command. The bits in the Error register have additional information regarding the cause of the error. 7. General Operational Requirements 7.1. Reset response A reset is accepted within 400 nsec after the negation of RESET- or within 400 nsec after SRST has been set in the Device Control register. When the drive is reset by RESET-, Drive 1 shall indicate it is present by asserting DASP- within 400 msec, and DASP- shall remain asserted for 30 seconds or until Drive 1 accepts the first command. See also 6.3.4 and 6.3.13. When the drive is reset by SRST, the drive shall set BSY=1. See also 7.2.6. When a reset is accepted, and with BSY set: a) Both drives perform any necessary hardware initialization b) Both drives clear any previously programmed drive parameters c) Both drives may revert to the default condition d) Both drives load the Command Block Registers with their default values e) If a hardware reset, Drive 0 waits for DASP- to be asserted by Drive 1 f) If operational, Drive 1 asserts DASP- g) Drive 0 waits for PDIAG- to be asserted if Drive 1 asserts DASP- h) If operational, Drive 1 clears BSY i) If operational, Drive 1 asserts PDIAG- j) Drive 0 clears BSY No interrupt is generated when initialization is complete. The default values for the Command Block Registers if no self-tests are performed or if no errors occurred are: ERROR = 01h CYLINDER LOW = 00h SECTOR COUNT = 01h CYLINDER HIGH = 00h SECTOR NUMBER = 01h DRIVE/HEAD = 00h The Error register shall contain a DIAGNOSTIC CODE (see table 10) if a self-test is performed. Following any reset, the host should issue an INITIALIZE DRIVE PARAMETERS command to ensure the drive is initialized as desired. There are three types of reset in ATA. The following is a suggested method of classifying reset actions: * Power On Reset: the drive executes a series of electrical circuitry diagnostics, spins up the HDA, tests speed and other mechanical parametrics, and sets default values. * Hardware Reset: the drive executes a series of electrical circuitry diagnostics, and resets to default values. * Software Reset: the drive resets the interface circuitry according to the Set Features requirement (See 9.22) 7.2. Translate mode The cylinder, head and sector geometry of the drive as presented to the host may differ from the actual physical geometry. Translate mode is an optional and device specific means of mapping between the two. 7.3. Power conditions Optional power commands permit the host to modify the behavior of the drive in a manner which reduces the power required to operate. +==========-====-=====-====-==================-=====+ | Mode |SRST| BSY |DRDY| Interface active |Media| |----------+----+-----+----+------------------+-----| | Sleep | * | x | x | * | I | | | | | | | | | Standby | x | 0 | 1 | Yes | I | | | | | | | | | Idle | x | 0 | 1 | Yes | A | | | | | | | | | Active | x | x | x | Yes | A | |---------------------------------------------------| | A = Active I = Inactive * See 9.23 | +===================================================+ Table 7 - Power Conditions The lowest power consumption when the drive is powered on occurs in Sleep Mode. When in Sleep Mode, the drive requires a reset to be activated (see 9.23). The time to respond could be as long as 30 seconds. In Standby Mode the drive interface is capable of accepting commands, but as the media is not immediately accessible, it could take the drive as long as 30 seconds to respond. In Idle Mode the drive is capable of responding immediately to media access requests. A drive in Idle Mode may take longer to complete the execution of a command because it may have to activate some circuitry. In Active mode the drive is capable of responding immediately to media access requests, and commands complete execution in the shortest possible time. Ready is not a power condition. A drive may post ready at the interface even though the media may not be accessible. See specific power-related commands. 7.4. Error posting The errors that are valid for each command are defined in table 8. It is not a requirement that all valid conditions be implemented. See 7.2.9 and 7.2.13 for the definition of the Error register and Status register bits. +===========================-============================-=====================+ | | Error register | Status register | |---------------------------+----------------------------+---------------------| | |BBK|UNC|IDNF|ABRT|TK0NF|AMNF|DRDY|DWF|DSC|CORR|ERR| |---------------------------+---+---+----+----+-----+----+----+---+---+----+---| | ACKNOWLEDGE MEDIA CHANGE | | | | V | | | | | | | V | | BOOT - POST-BOOT | | | | V | | | | | | | V | | BOOT - PRE-BOOT | | | | V | | | | | | | V | | CHECK POWER MODE | | | | V | | | V | V | V | | V | | DOOR LOCK | | | V | V | | | V | | | | V | | DOOR UNLOCK | | | | V | | | | | | | V | | Download Microcode | | | | V | | | V | V | V | | V | | |----------------------------| | | | | | | Execute drive diags | See 9.7 | | | | | V | | |----------------------------| | | | | | | FORMAT TRACK | | | V | V | | | V | V | V | | V | | IDENTIFY DRIVE | | | | V | | | V | V | V | | V | | IDLE | | | | V | | | V | V | V | | V | | IDLE IMMEDIATE | | | | V | | | V | V | V | | V | | Initialize drive parms | | | | | | | V | V | V | | | | NOP | | | | V | | | | | | | V | | READ BUFFER | | | | V | | | V | V | V | | V | | READ DMA | V | V | V | V | | V | V | V | V | V | V | | READ LONG | V | | V | V | | V | V | V | V | | V | | READ MULTIPLE | V | V | V | V | | V | V | V | V | V | V | | READ SECTOR(S) | V | V | V | V | | V | V | V | V | V | V | | READ VERIFY SECTOR(S) | V | V | V | V | | V | V | V | V | V | V | | RECALIBRATE | | | | V | V | | V | V | V | | V | | SEEK | | | V | V | | | V | V | V | | V | | SET FEATURES | | | | V | | | V | V | V | | V | | SET MULTIPLE MODE | | | | V | | | V | V | V | | V | | SLEEP | | | | V | | | V | V | V | | V | | STANDBY | | | | V | | | V | V | V | | V | | STANDBY IMMEDIATE | | | | V | | | V | V | V | | V | | WRITE BUFFER | | | | V | | | V | V | V | | V | | WRITE DMA | V | | V | V | | | V | V | V | | V | | WRITE LONG | V | | V | V | | | V | V | V | | V | | WRITE MULTIPLE | V | | V | V | | | V | V | V | | V | | WRITE SAME | V | | V | V | | | V | V | V | | V | | WRITE SECTOR(S) | V | | V | V | | | V | V | V | | V | | WRITE VERIFY | V | V | V | V | | V | V | V | V | V | V | |---------------------------+---+---+----+----+-----+----+----+---+---+----+---| | Invalid command code | | | | V | | | V | V | V | | V | |------------------------------------------------------------------------------| | V = valid on this command | +==============================================================================+ Table 8 - Register Usage 8. Command Descriptions Commands are issued to the drive by loading the pertinent registers in the command block with the needed parameters, and then writing the command code to the Command register. The manner in which a command is accepted varies. There are three classes (see table 9) of command acceptance, all predicated on the fact that to receive a command, BSY=0: * Upon receipt of a Class 1 command, the drive sets BSY within 400 nsec. * Upon receipt of a Class 2 command, the drive sets BSY within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 700 usec, and clears BSY within 400 nsec of setting DRQ. * Upon receipt of a Class 3 command, the drive sets BSY within 400 nsec, sets up the sector buffer for a write operation, sets DRQ within 20 msec, and clears BSY within 400 nsec of setting DRQ. NOTE 8 DRQ may be set so quickly on Class 2 and Class 3 that the BSY transition is too short for BSY=1 to be recognized. The drive shall implement all mandatory commands as identified by an M, and may implement the optional commands identified by an O, in table 9. V indicates a Vendor Specific command code. If a new command is issued to a drive which has an uncompleted command (subsequently referred to as Old Command) in progress, the drive shall immediately respond to the new command (Subsequently referred to as New Command), even if execution of the Old Command could have been completed. There shall be no indication given to the system as to the status of the Old Command which was being executed at the time the New Command was issued. +=====-======================================-Command-=====Parameters Used====+ |Class| | code | FR | SC | SN | CY | DH | |-----+--------------------------------------+-------+----+----+----+----+----| | 1 | ACKNOWLEDGE MEDIA CHANGE | O | DBh | | | | | D | | 1 | BOOT - POST-BOOT | O | DCh | | | | | D | | 1 | BOOT - PRE-BOOT | O | DDh | | | | | D | | 1 | CHECK POWER MODE | O |98h E5h| | y | | | D | | 1 | DOOR LOCK | O | DEh | | | | | D | | 1 | DOOR UNLOCK | O | DFh | | | | | D | | 3 | Download Microcode | O | 92h | y | y | y | y | D | | 1 | EXECUTE DRIVE DIAGNOSTIC | M | 90h | | | | | D*| | 2 | FORMAT TRACK | M | 50h | * | y | | y | y | | 1 | IDENTIFY DRIVE | O | ECh | | | | | D | |-----+-----------------------------------------------------------------------| | | CY = Cylinder registers SC = Sector Count register | | | DH = Drive/Head register SN = Sector Number register | | | FR = Features register (see command descriptions for use) | | | y - the register contains a valid parameter for this command. | | | For the Drive/Head register, y means both the drive and | | | head parameters are used. | | | D - only the drive parameter is valid and not the head parameter. | | | D* - Addressed to drive 0 but both drives execute it. | | | * - Maintained for compatibility (see 7.2.10) | +=============================================================================+ Table 9 - Command Codes and Parameters (Part 1 of 2) +=====-======================================-Command-=====Parameters Used====+ |Class| | code | FR | SC | SN | CY | DH | |-----+--------------------------------------+-------+----+----+----+----+----| | 1 | IDLE | O |97h E3h| | y | | | D | | 1 | IDLE IMMEDIATE | O |95h E1h| | | | | D | | 1 | INITIALIZE DRIVE PARAMETERS | M | 91h | | y | | | y | | 1 | NOP | O | 00h | | | | | y | | 1 | READ BUFFER | O | E4h | | | | | D | | 1 | READ DMA (w/retry) | O | C8h | | y | y | y | y | | 1 | READ DMA (w/o retry) | O | C9h | | y | y | y | y | | 1 | READ LONG (w/retry) | M | 22 | | y | y | y | y | | 1 | READ LONG (w/o retry) | M | 23 | | y | y | y | y | | 1 | READ MULTIPLE | O | C4h | | y | y | y | y | | 1 | READ SECTOR(S) (w/retry) | M | 20 | | y | y | y | y | | 1 | READ SECTOR(S) (w/o retry) | M | 21 | | y | y | y | y | | 1 | READ VERIFY SECTOR(S) (w/retry) | M | 40 | | y | y | y | y | | 1 | READ VERIFY SECTOR(S) (w/o retry)| M | 41 | | y | y | y | y | | 1 | RECALIBRATE | M | 1xh | | | | | D | | 1 | SEEK | M | 7xh | | | y | y | y | | 1 | SET FEATURES | O | EFh | y | | | | D | | 1 | SET MULTIPLE MODE | O | C6h | | y | | | D | | 1 | SLEEP | O |99h E6h| | | | | D | | 1 | STANDBY | O |96h E2h| | y | | | D | | 1 | STANDBY IMMEDIATE | O |94h E0h| | | | | D | | 2 | WRITE BUFFER | O | E8h | | | | | D | | 3 | WRITE DMA (w/retry) | O | CAh | | y | y | y | y | | 3 | WRITE DMA (w/o retry) | O | CBh | | y | y | y | y | | 2 | WRITE LONG (w/retry) | M | 32 | * | y | y | y | y | | 2 | WRITE LONG (w/o retry) | M | 33 | * | y | y | y | y | | 3 | WRITE MULTIPLE | O | C5h | * | y | y | y | y | | 3 | WRITE SAME | O | E9h | y | y | y | y | y | | 2 | WRITE SECTOR(S) (w/retry) | M | 30 | * | y | y | y | y | | 2 | WRITE SECTOR(S) (w/o retry) | M | 31 | * | y | y | y | y | | 3 | WRITE VERIFY | O | 3Ch | * | y | y | y | y | | | Vendor unique | V | 9Ah | | | | | | | | Vendor unique | V | C0-C3h| | | | | | | | Vendor unique | V | 8xh | | | | | | | | Vendor unique | V |F0h-FFh| | | | | | | | Reserved: all remaining codes | | | | | | | | |-----+-----------------------------------------------------------------------| | | CY = Cylinder registers SC = Sector Count register | | | DH = Drive/Head register SN = Sector Number register | | | FR = Features register (see command descriptions for use) | | | y - the register contains a valid parameter for this command. | | | For the Drive/Head register, y means both the drive and | | | head parameters are used. | | | D - only the drive parameter is valid and not the head parameter. | | | D* - Addressed to drive 0 but both drives execute it. | | | * - Maintained for compatibility (see 7.2.10) | +=============================================================================+ Table 9 - Command Codes and Parameters (Part 2 of 2) 8.1. ACKNOWLEDGE MEDIA CHANGE (removable) If the drive is operating in a mode which requires that the operating system acknowledge a media change, this command clears the Media Change Error so that normal operation can resume. If the drive is not operating in such a mode, this command returns an Abort error. 8.2. BOOT - POST-BOOT (removable) This command provides a means to send vendor-specific information that may be required in order to pass diagnostics which are applicable to non-removable disk drives. 8.3. BOOT - PRE-BOOT (removable) This command is issued to prepare a removable drive to respond to boot. 8.4. CHECK POWER MODE This command checks the power mode. If the drive is in, going to, or recovering from the Standby Mode the drive shall set BSY, set the Sector Count register to 00h, clear BSY, and generate an interrupt. If the drive is in the Idle Mode, the drive shall set BSY, set the Sector Count register to FFh, clear BSY, and generate an interrupt. 8.5. DOOR LOCK (removable) This command locks the door if the drive is Ready and unlocked, otherwise it responds with Not Ready. 8.6. DOOR UNLOCK (removable) This command unlocks the door if the drive is Ready and locked, otherwise it responds with Not Ready. 8.7. Download Microcode This command enables the host to alter the drive's microcode. See 9.2 for the protocol. The head bits of the Drive/Head register shall always be set to zero. The data transferred using the Download Microcode command is vendor unique. All transfers shall be an integer multiple of the sector size. The size of the data transfer is determined by the contents of the Sector Register and the Sector Count register. The Sector Register shall be used to extend the Sector Count register, to create a sixteen bit SECTOR COUNT value. The Sector Register shall be the most significant eight bits and the Sector Count register shall be the least significant eight bits. A value of zero in both the Sector Register and the Sector Count register shall indicate no data is to be transferred. This allows transfer sizes from 0 bytes to 33 553 920 bytes, in 512 byte increments. The use of Cylinder High and Low registers is optional. If not used, these registers should be set to zero. However, if a vendor wishes to maintain multiple versions of microcode, then these registers may be use to select between the microcode versions. In this case, the meaning of the contents of these registers is Vendor Unique. The value of the Features register shall be used to determine the time the update takes effect, whether it is saved for future use, and how to manage more than one revision of microcode at a time: Replace Current (bit 0) - if set, then the specified microcode becomes the current operating microcode upon successful completion of the command. Replace Default (bit 1) - if set, then the specified microcode becomes default microcode. The drive shall default to this microcode upon power on and reset conditions. Save (bit 2) - if set, then the specified microcode is saved to nonvolatile memory. Retrieve (bit 3) - if set, then the specified microcode is made the current and/or default code according to bits 0 and 1. Note that any data transferred to the drive is ignored. Reserved (bits 4 - 7) Bite 2 and 3 cannot both be set at the same time. +---+---+---+---+-----------------------------------------------------------------+ |Bit|Bit|Bit|Bit| | | 3 | 2 | 1 | 0 | Operation | +---+---+---+---+-----------------------------------------------------------------+ | 0 | 0 | 0 | 0 | no-op | | 0 | 0 | 0 | 1 | download is for immediate, temporary use | | 0 | 0 | 1 | x | no-op | | 0 | 1 | 0 | 0 | save downloaded code for future reference by value of cyl | | 0 | 1 | 0 | 1 | save downloaded code for future reference by value of cyl | | | | | | and use immediately | | 0 | 1 | 1 | 0 | save downloaded code for future reference by value of cyl | | | | | | and specify it as the default for future use | | 0 | 1 | 1 | 1 | save downloaded code for future reference by value of cyl | | | | | | and specify it as the default for immediate and future use | | 1 | 0 | 0 | 0 | no-op | | 1 | 0 | 0 | 1 | retrieve saved code by value of cyl and use immediately | | 1 | 0 | 1 | 0 | retrieve saved code by value of cyl and specify it as the | | | | | | default for future use | | 1 | 0 | 1 | 1 | retrieve saved code by value of cyl and specify it as the | | | | | | default for immediate and future use | | 1 | 1 | x | x | no-op | +---+---+---+---+-----------------------------------------------------------------+ Note: in some implementations the default microcode may not be immediately available (e.g. may be stored on disk). However, it shall become effective before any media access command can be successfully executed. Table 10 - Features register Values for Download Microcode 8.8. EXECUTE DRIVE DIAGNOSTIC This command shall perform the internal diagnostic tests implemented by the drive. See also 6.3.4 and 6.3.13. The DRV bit is ignored. Both drives, if present, shall execute this command. If Drive 1 is present: * Drive 1 asserts PDIAG- within 5 seconds. * Drive 0 waits up to 6 seconds for Drive 1 to assert PDIAG-. * If Drive 1 has not asserted PDIAG-, indicating a failure, Drive 0 shall append 80h to its own diagnostic status. * Both drives shall execute diagnostics. * If Drive 1 diagnostic failure is detected when Drive 0 status is read, * Drive 1 status is obtained by setting the DRV bit, and reading status. If there is no Drive 1 present: * Drive 0 posts only its own diagnostic results. * Drive 0 clears BSY, and generates an interrupt. The Diagnostic Code written to the Error register is a unique 8-bit code as shown in table 10, and not as the single bit flags defined in 7.2.9. If Drive 1 fails diagnostics, Drive 0 "OR's" 80h with its own status and loads that code into the Error register. If Drive 1 passes diagnostics or there is no Drive 1 connected, Drive 0 "OR's" 00h with its own status and loads that code into the Error register. +=======-==================================+ | Code | | |-------+----------------------------------| | 01h | No error detected | | 02h | Formatter device error | | 03h | Sector buffer error | | 04h | ECC circuitry error | | 05h | Controlling microprocessor error | | 8xh | Drive 1 failed | +==========================================+ Table 11 - Diagnostic Codes 8.9. FORMAT TRACK The implementation of the FORMAT TRACK command is vendor specific. The actions may be a physical reformatting of a track, initializing the data field contents to some value, or doing nothing. The Sector Count register contains the number of sectors per track. The track address is specified in the Cylinder High and Cylinder Low registers, and the number of sectors is specified in the Sector Count register. When the command is accepted, the drive sets the DRQ bit and waits for the host to fill the sector buffer. When the sector buffer is full, the drive clears DRQ, sets BSY and begins command execution. The contents of the sector buffer shall not be written to the media, and may be either ignored or interpreted as follows: +=============-=============-=============-==========================+ |DD15 ---- DD0| |DD15 ---- DD0| | |-------------| |-------------+--------------------------| | First sector| | Last sector | Remainder of buffer | | descriptor | : : : : : : | descriptor | filled with zeros | +====================================================================+ Figure 4 - Format Track Data Field Format One 16-bit word represents each sector, the words being contiguous from the start of a sector. Any words remaining in the buffer after the representation of the last sector are filled with zeros. DD15-8 contain the SECTOR NUMBER. If an interleave is specified, the words appear in the same sequence as they appear on the track. DD7-0 contain a descriptor value defined as follows: 00h - Format sector as good 20h - Unassign the alternate location for this sector 40h - Assign this sector to an alternate location 80h - Format sector as bad NOTE 9 Some users of the ATA drive expect the operating system partition table to be erased on a Format command. It is recommended that a drive which does not perform a physical format of the track, write a data pattern of all zeros to the sectors which have been specified by the FORMAT TRACK command. NOTE 10 It is recommended that implementors reassign data blocks which show repeated errors. 8.10. IDENTIFY DRIVE The IDENTIFY DRIVE command enables the host to receive parameter information from the drive. When the command is issued, the drive sets BSY, stores the required parameter information in the sector buffer, sets DRQ, and generates an interrupt. The host then reads the information out of the sector buffer. The parameter words in the buffer have the arrangement and meanings defined in Table 11. All reserved bits or words shall be zero. +=======-==================================================================+ | Word | | |-------+------------------------------------------------------------------| | 0 | General configuration bit-significant information: | | | 15 0 reserved for non-magnetic drives | | | 14 1=format speed tolerance gap required | | | 13 1=track offset option available | | | 12 1=data strobe offset option available | | | 11 1=rotational speed tolerance is > 0,5% | | | 10 1=disk transfer rate > 10 Mbs | | | 9 1=disk transfer rate > 5Mbs but <= 10Mbs | | | 8 1=disk transfer rate <= 5Mbs | | | 7 1=removable cartridge drive | | | 6 1=fixed drive | | | 5 1=spindle motor control option implemented | | | 4 1=head switch time > 15 usec | | | 3 1=not MFM encoded | | | 2 1=soft sectored | | | 1 1=hard sectored | | | 0 0=reserved | | 1 | Number of cylinders | | 2 | Reserved | | 3 | Number of heads | | 4 | Number of unformatted bytes per track | | 5 | Number of unformatted bytes per sector | | 6 | Number of sectors per track | | 7-9 | Vendor unique | | 10-19 | Serial number (20 ASCII characters, 0000h=not specified) | | 20 | Buffer type | | 21 | Buffer size in 512 byte increments (0000h=not specified) | | 22 | # of ECC bytes avail on READ/WRITE LONG cmds (0000h=not spec'd) | | 23-26 | Firmware revision (8 ASCII characters, 0000h=not specified) | | 27-46 | Model number (40 ASCII characters, 0000h=not specified) | | 47 | 15-8 Vendor unique | | | 7-0 00h = READ/WRITE MULTIPLE commands not implemented | | | xxh = Maximum number of sectors that can be transferred | | | per interrupt on READ AND WRITE MULTIPLE commands | | 48 | 0000h = cannot perform doubleword I/O Included for backwards | | | 0001h = can perform doubleword I/O Compatible VU use | +==========================================================================+ Table 12 - Identify Drive Information (Part 1 of 2) +=======-==================================================================+ | Word | | |-------+------------------------------------------------------------------| | 49 | Capabilities | | | 15-13 0=reserved | | | 12 1=Reserved (for advanced PIO mode support) | | | 11 1=IORDY Supported | | | 10 1=IORDY can be disabled | | | 9 1=LBA supported | | | 8 1=DMA supported | | | 7- 0 Vendor unique | | 50 | Reserved | | 51 | 15-8 PIO data transfer cycle timing mode | | | 7-0 Vendor unique | | 52 | 15-8 DMA data transfer cycle timing mode | | | 7-0 Vendor unique | | 53 | 15-2 Reserved | | | 1 1=the fields reported in words 64-70 are valid | | | 0=the fields reported in words 64-70 are not valid | | | 0 1=the fields reported in words 54-58 are valid | | | 0=the fields reported in words 54-58 may be valid | | 54 | Number of current cylinders | | 55 | Number of current heads | | 56 | Number of current sectors per track | | 57-58 | Current capacity in sectors | | 59 | 15-9 Reserved | | | 8 1 = Multiple sector setting is valid | | | 7-0 xxh = Current setting for number of sectors that can be | | | transferred per interrupt on R/W multiple commands | | 60-61 | Total number of user addressable sectors (LBA mode only) | | 62 | 15-8 Single word DMA transfer mode active | | | 7-0 Single word DMA transfer modes supported (see 11-3a) | | 63 | 15-8 Multiword DMA transfer mode active | | | 7-0 Multiword DMA transfer modes supported (see 11-3b) | | 64 | 15-8 Reserved | | | 7-0 Advanced PIO Transfer Modes Supported | | 65 | Minimum Multiword DMA Transfer Cycle Time Per Word | | | 15-0 Cycle time in nanoseconds | | 66 | Manufacturer's Recommended Multiword DMA Transfer Cycle Time | | | 15-0 Cycle time in nanoseconds | | 67 | Minimum PIO Transfer Cycle Time Without Flow Control | | | 15-0 Cycle Time in nanoseconds | | 68 | Minimum PIO Transfer Cycle Time With IORDY Flow Control | | | 15-0 Cycle Time in nanoseconds | | 69-70 | Reserved (for advanced PIO mode support) | | 71-127| Reserved | |128-159| Vendor unique | |160-255| Reserved | +==========================================================================+ Table 12 - Identify Drive Information (Part 2 of 2) The fields described in 9.9.1 through 9.9.5 are not affected by the INITIALIZE DRIVE PARAMETERS command. 8.10.1. Word 1: Number of cylinders The number of user-addressable cylinders in the default translation mode. 8.10.2. Word 3: Number of heads The number of user-addressable heads in the default translation mode. 8.10.3. Word 4: Number of unformatted bytes per track The number of unformatted bytes per translated track in the default translation mode. 8.10.4. Word 5: Number of unformatted bytes per sector The number of unformatted bytes per sector in the default translation mode. 8.10.5. Word 6: Number of sectors per track The number of user-addressable sectors per track in the default translation mode. 8.10.6. Word 10-19: Serial Number The contents of this field are right justified and padded with spaces (20h). 8.10.7. Word 20: Buffer Type The contents of the field are determined by the manufacturer. 0000h not specified. 0001h a single ported single sector buffer which is not capable of simultaneous data transfers to or from the host and the disk. 0002h a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the disk. 0003h a dual ported multi-sector buffer capable of simultaneous transfers with a read caching capability. 0004-FFFFh reserved These codes are typically not used by the operating system, however, they are useful for diagnostic programs which perform initialization routines e.g. a different interleave may be desirable for 0001h vs. 0002h or 0003h. 8.10.8. Word 22: ECC bytes available on READ/WRITE LONG commands If the contents of this field are set to a value other than 4, the only way to use this information is via the SET FEATURES commands. 8.10.9. Word 23-26: Firmware revision The contents of this field are left justified an padded with spaces (20h). 8.10.10. Word 27-46: Model number The contents of this field are left justified and padded with spaces (20h). 8.10.11. Word 49 8.10.12. IORDY Support Bit 11 of word 49, the Capabilities word, is used to help determine whether a device supports IORDY. If this bit is set to one, then the device supports IORDY operation. If this bit is zero, the device may support IORDY. This insures backward compatibility. If a device supports PIO Mode 3, then this bit must be set. 8.10.13. IORDY Can Be Disabled Bit 10 of word 49, the Capabilities word, is used to indicate a devices ability to enable or disable the use of IORDY. If this bit is set to one, then the device supports the disabling of IORDY. 8.10.14. Word 51: PIO data transfer cycle timing mode The PIO transfer timing for each ATA device falls into categories which have unique parametric timing specifications. To determine the proper device timing category, compare the Cycle Time specified in figure 6 with the contents of this field. The value returned in Bits 15-8 should fall into one of the categories specified in figure 6, and if it does not, then Mode 0 shall be used to serve as the default timing. 8.10.15. Word 52: DMA data transfer cycle timing mode The DMA transfer timing for each ATA device falls into categories which have unique parametric timing specifications. To determine the proper device timing category, compare the Cycle Time specified in figure 6 with the contents of this field. The value returned in Bits 15-8 should fall into one of the categories specified in figure 6, and if it does not, then Mode 0 shall be used to serve as the default timing. The contents of this word shall be ignored if Words 62 or 63 are supported. 8.10.16. Word 53: Field Validity Word 53, bit 0 defines whether the fields contained in words 54 through 58 are guaranteed to be valid. If this bit is not set, the fields contained in words 54 through 58 may be valid. Word 53, bit 1 will be set if any of the fields reported in words 64 through 70 are valid. This bit will be reset if the fields reported in words 64-70 are not valid. Any device which supports PIO Mode 3 or above, or supports Multiword DMA Mode 1 or above, must set bit 1 of word 53 and support the fields contained in words 64 through 70. 8.10.17. Word 54: Number of current cylinders The number of user-addressable cylinders in the current translation mode. 8.10.18. Word 55: Number of current heads The number of user-addressable heads in the current translation mode. 8.10.19. Word 56: Number of current sectors per track The number of user-addressable sectors per track in the current translation mode. 8.10.20. Word 57-58: Current capacity in sectors The current capacity in sectors excludes all sectors used for device-specific purposes. The number of sectors of available capacity may be calculated as: (Number of current cylinders * Number of current heads * Number of current sectors per track) 8.10.21. Word 59: Multiple sector setting If the valid bit is set, then bits 7-0 reflect the number of sectors currently set to transfer on a READ OR WRITE MULTIPLE command. 8.10.22. Word 60-61: Total number of user addressable sectors If the drive supports LBA Mode, these words reflect the total number of user addressable sectors. This value does not depend on the current drive geometry. If the drive does not support LBA mode, these words shall be set to 0. 8.10.23. Word 62: Single word DMA transfer The low order byte identifies by bit all of the Modes which are supported e.g. if Mode 0 is supported, bit 0 is set. The high order byte contains a single bit set to indicate which mode is active. 8.10.24. Word 63: Multiword DMA transfer The low order byte identifies by bit all of the Modes which are supported e.g. if Mode 0 is supported, bit 0 is set. The high order byte contains a single bit set to indicate which mode is active. 8.10.25. Word 64: Flow Control PIO Transfer Modes Supported Bits 7 through 0 of word 64 of the Identify Drive parameter information is defined as the Advanced PIO Data Transfer Supported Field. This field is bit significant. Any number of bits may be set in this field by the device to indicate which Advanced PIO Modes that it is capable of supporting. Of these bits, bits 7 through 1 are Reserved for future Advanced PIO Modes. Bit 0, if set, indicates that the device supports PIO Mode 3. 8.10.26. Word 65: Minimum Multiword DMA Transfer Cycle Time Per Word Word 65 of the parameter information of the IDENTIFY DRIVE command is defined as the Minimum Multiword DMA Transfer Cycle Time Per Word. This field defines, in nanoseconds, the minimum cycle time that the device can support when performing Multiword DMA transfers on a per word basis. If this field is supported, bit 1 of word 53 must be set. Any device which supports Multiword DMA Mode 1 or above shall support this field, and the value in word 65 shall not be less that 150. If bit 1 of word 53 is set and the device does not support this field, the device shall return a value of zero in this field. 8.10.27. Word 66: Manufacturer's Recommended Multiword DMA Transfer Cycle Time Word 66 of the parameter information of the IDENTIFY DRIVE command is defined as the Manufacturer's Recommended Multiword DMA Transfer Cycle Time. This field defines, in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA commands over all locations on the media under nominal conditions. A cycle time less that this value may cause DMARQ to be deasserted at a rate which may reduce throughput, without data corruption. If this field is supported, bit 1 of word 53 must be set. Any device which supports Multiword DMA Mode 1 or above shall support this field, and the value in word 66 shall not be less than the value in word 65. If bit 1 of word 53 is set and the device does not support this field, the device shall return a value of zero in this field. 8.10.28. Word 67: Minimum PIO Transfer Cycle Time Without Flow Control Word 67 of the parameter information of the IDENTIFY DRIVE command is defined as the Minimum PIO Transfer Without Flow Control Cycle Time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the device guarantees data integrity during the transfer without utilization of flow control. Any device may support this field, and if this field is supported, Bit 1 of word 53 shall be set. Any device which supports PIO Mode 3 or above must support this field, and the value in word 67 shall not be less that 180. If Bit 1 of word 53 is set and the device does not support this field, the device shall return a value of zero in this field. 8.10.29. Word 68: Minimum PIO Transfer Cycle Time With IORDY Flow Control Word 68 of the parameter information of the IDENTIFY DRIVE command is defined as the Minimum PIO Transfer With IORDY Flow Control Cycle Time. This field defines, in nanoseconds, the minimum cycle time that the device can support while performing data transfers while utilizing IORDY flow control. Any device may support this field, and if this field is supported, Bit 1 of word 53 must be set. Any device which supports PIO Mode 3 or above must support this field, and the value in word 68 shall not be less that 180. If Bit 1 of word 53 is set and the device does not support this field, the device shall return a value of zero in this field. 8.10.30. Words 69 and 70 Words 69 and 70 are reserved for future definition. (Editor's note: It is intended that this field be used for future specification of an alternative flow control mechanism, currently being referred to as advanced PIO flow control.) 8.11. IDLE This command causes the drive to set BSY, enter the Idle Mode, clear BSY, and generate an interrupt. The interrupt is generated even though the drive may not have fully transitioned to Idle Mode. If the drive is already spinning, the spin up sequence is not executed. If the Sector Count register is non-zero then the Automatic Idle Mode sequence shall be enabled. The value in the Sector Count register shall be used to determine the Automatic Idle Mode Timeout period. If the Sector Count register is zero then the Automatic Idle Mode sequence shall be disabled. If the device is in the Active Mode and the Automatic Idle Mode sequence is enabled, then the device shall begin an Automatic Idle Mode Timeout at the completion of any command or all tasks related to commands previously received. If the Automatic Idle Mode Timeout period elapses, the device shall enter the Idle Mode. The value in the Sector Count register when the IDLE command is issued shall determine the period of the Automatic Idle Mode Timeout. See Table xx. +---------------------+------------------------------+ | Sector Count | Corresponding | | Register contents | Timeout Period | +---------------------+------------------------------+ | 0 (00h) | Timeout Disabled | | 1 - 240 (01h-F0h) | (value * 5) seconds | | 241 - 251 (F1h-FBh) | ((value - 240) * 30) minutes | | 252 (FCh) | 21 minutes | | 253 - 254 (FDh-FEh) | ((value * 6) hours | | 255 (FFh) | 21 minutes 15 seconds | +---------------------+------------------------------+ Table 13 - Automatic Timeout Periods 8.12. IDLE IMMEDIATE This command causes the drive to set BSY, enter the Idle Mode, clear BSY, and generate an interrupt. The interrupt is generated even though the drive may not have fully transitioned to Idle Mode. 8.13. INITIALIZE DRIVE PARAMETERS This command enables the host to set the number of sectors per track and the number of heads minus 1, per cylinder. Upon receipt of the command, the drive sets BSY, saves the parameters, clears BSY, and generates an interrupt. The only two register values used by this command are the Sector Count register which specifies the number of sectors per track, and the Drive/Head register which specifies the number of heads minus 1. The DRV bit designates these values to Drive 0 or Drive 1, as appropriate. The SECTOR COUNT and head values are not checked for validity by this command. If they are invalid, no error will be posted until an illegal access is made by some other command. 8.14. NOP This command enables a host which can only perform 16-bit register accesses to check drive status. The drive shall respond as it does to an unrecognized command by setting Abort in the Error register, Error in the Status register, clearing Busy in the Status register, and asserting INTRQ. NOTE 11 When a 16-bit host writes to the Drive/Head Register, one byte contains the Command register, so the drive sees a new command when the intended purpose is only to select a drive. Both drives may be Busy but not necessarily Ready, e.g. Drive 0 may be ready, but not drive 1. To check this possibility a typical sequence for an 8-bit host would be: a) Read the Status register (wait until Busy False) b) Select the drive (write to the Drive/Head Register) c) Read the Status register (wait until Busy False and Ready True) d) Send the command (write to the Command register). As a 16-bit host executes b and d simultaneously, a problem occurs if the drive being selected is Not Ready at the time the command is issued. 8.15. READ BUFFER The READ BUFFER command enables the host to read the current contents of the drive's sector buffer. When this command is issued, the drive sets BSY, sets up the sector buffer for a read operation, sets DRQ, clears BSY, and generates an interrupt. The host then reads up to 512 bytes of data from the buffer. The READ BUFFER and WRITE BUFFER commands shall be synchronized such that sequential WRITE BUFFER and READ BUFFER commands access the same 512 bytes within the buffer. 8.16. READ DMA This command executes in a similar manner to the READ SECTOR(S) command except for the following: * the host initializes a slave-DMA channel prior to issuing the command * data transfers are qualified by DMARQ and are performed by the slave-DMA channel * the drive issues only one interrupt per command to indicate that data transfer has terminated and status is available. Any unrecoverable error encountered during execution of a READ DMA command results in the termination of data transfer after the transfer of all sectors prior to the sector where the error was detected. The sector in error is not transferred. The drive generates an interrupt to indicate that data transfer has terminated and status is available. The error posting is the same as that of the READ SECTOR(S) command. 8.17. READ LONG The READ LONG command performs similarly to the READ SECTOR(S) command except that it returns the data and the ECC bytes appended to the data field of the desired sector. During a READ LONG command, the drive does not check the ECC bytes to determine if there has been a data error. Only single sector read long operations are supported. The transfer of the ECC bytes shall be one byte at a time over bits DD0-7 only (8- bits wide). 8.18. READ MULTIPLE command The READ MULTIPLE command performs similarly to the READ SECTOR(S) command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a SET MULTIPLE MODE command. Command execution is identical to the READ SECTOR(S) operation except that the number of sectors defined by a SET MULTIPLE MODE command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SET MULTIPLE MODE command, which shall be executed prior to the READ MULTIPLE command. When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer shall be for n sectors, where n = Remainder (SECTOR COUNT / block count) If the READ MULTIPLE command is attempted before the SET MULTIPLE MODE command has been executed or when READ MULTIPLE commands are disabled, the READ MULTIPLE operation shall be rejected with an Aborted Command error. Disk errors encountered during READ MULTIPLE commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer shall take place as it normally would, including transfer of corrupted data, if any. The contents of the Command Block Registers following the transfer of a data block which had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. 8.19. READ SECTOR(S) This command reads from 1 to 256 sectors as specified in the Sector Count register. A SECTOR COUNT of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number register. See 10.1 for the DRQ, IRQ and BSY protocol on data transfers. If the drive is not already on the desired track, an implied seek is performed. Once at the desired track, the drive searches for the appropriate ID field. If retries are disabled and two index pulses have occurred without error free reading of the requested ID, an ID Not Found error is posted. If retries are enabled, up to a vendor specific number of attempts may be made to read the requested ID before posting an error. If the ID is read correctly, the data address mark shall be recognized within a specified number of bytes, or the Address Mark Not Found error is posted. DRQ is always set prior to data transfer regardless of the presence or absence of an error condition. At command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector read. If an error occurs, the read terminates after the transfer of all sectors prior to the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer. 8.20. READ VERIFY SECTOR(S) This command is identical to the READ SECTOR(S) command, except that DRQ is never set, and no data is transferred to the host. See 10.3 for protocol. When the command is accepted, the drive sets BSY. When the requested sectors have been verified, the drive clears BSY and generates an interrupt. Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector verified. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The Sector Count register shall contain the number of sectors not yet verified. 8.21. RECALIBRATE This command moves the read/write heads from anywhere on the disk to cylinder 0. Upon receipt of the command, the drive sets BSY and issues a seek to cylinder zero. The drive then waits for the seek to complete before updating status, clearing BSY and generating an interrupt. If the drive cannot reach cylinder 0, a Track Not Found error is posted. 8.22. SEEK This command initiates a seek to the track and selects the head specified in the command block. The drive need not be formatted for a seek to execute properly. See 10.3 for protocol. The drive shall not set DSC=1 until the action of seeking has completed. The drive may return the interrupt before the seek is completed. If another command is issued to the drive while a seek is being executed, the drive sets BSY=1, waits for the seek to complete, and then begins execution of the command. 8.23. SET FEATURES This command is used by the host to establish the following parameters which affect the execution of certain drive features as shown in table 12. +=====-=============================================================+ | 01h | Enable 8-bit data transfers (see 6.3.5) | | 02h | Enable write cache * | | 03h | Set transfer mode based on value in Sector Count register | | 33h | Disable retry * | | 44h | Vendor unique length of ECC on READ LONG/WRITE LONG commands| | 54h | Set cache segments to Sector Count register value * | | 55h | Disable read look-ahead feature | | 66h | Disable reverting to power on defaults (see 9.22) | | 77h | Disable ECC * | | 81h | Disable 8-bit data transfers (see 6.3.5) | | 82h | Disable write cache * | | 88h | Enable ECC * | | 99h | Enable retries * | | AAh | Enable read look-ahead feature | | ABh | Set maximum prefetch using Sector Count register value * | | BBh | 4 bytes of ECC apply on READ LONG/WRITE LONG commands | | CCh | Enable reverting to power on defaults (see 9.22) | |-----+-------------------------------------------------------------| | | *These feature definitions are vendor-specified | +===================================================================+ Table 14 - Set Features register Definitions See 10.3 for protocol. If the value in the register is not supported or is invalid, the drive posts an Aborted Command error. At power on, or after a hardware reset, the default mode is the same as that represented by values greater than 80h. A setting of 66h allows settings of greater than 80h which may have been modified since power on to remain at the same setting after a software reset. A host can choose the transfer mechanism by Set Transfer Mode and specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. PIO Default Transfer Mode 00000 000 PIO Default Transfer Mode, Disable IORDY 00000 001 PIO Flow Control Transfer Mode x 00001 nnn Single Word DMA Mode x 00010 nnn Multiword DMA Mode x 00100 nnn Reserved 01000 nnn where "n" or "nnn" is a valid mode number for the associated transfer type. (Editor's note: It is intended that the reserved values be used for future specification of an alternative flow control mechanism.) If a device does not support the mode specified, the device posts an Aborted Command error. If a device supports this specification, and receives a SET FEATURES command with a Set Transfer Mode parameter and a Sector Count register value of "00000 000", it shall set its default PIO transfer mode. If the value is "00000 001" and the device supports disabling of IORDY, then the device shall set its default PIO transfer mode and disable IORDY. See vendor specification for the default mode of the commands which are vendor- specified. Peripherals reporting support for Multi Word DMA Transfer Mode 1 must also support Multi Word DMA Transfer Mode 0. Support of IORDY is mandatory when PIO Mode 3 is the current mode of operation. 8.24. SET MULTIPLE MODE This command enables the drive to perform READ AND WRITE MULTIPLE operations and establishes the block count for these commands. See 10.3 for protocol. The Sector Count register is loaded with the number of sectors per block. Drives shall support block sizes of 2, 4, 8, and 16 sectors, if their buffer size is at least 8,192 bytes, and may also support other block sizes. Upon receipt of the command, the drive sets BSY=1 and checks the Sector Count register. If the Sector Count register contains a valid value and the block count is supported, the value is loaded for all subsequent READ MULTIPLE and WRITE MULTIPLE commands and execution of those commands is enabled. If a block count is not supported, an Aborted Command error is posted, and READ MULTIPLE and WRITE MULTIPLE commands are disabled. If the Sector Count register contains 0 when the command is issued, READ AND WRITE MULTIPLE commands are disabled. At power on, or after a hardware reset, the default mode is READ AND WRITE MULTIPLE disabled. If Disable Default has been set in the Features register then the mode remains the same as that last established prior to a software reset, otherwise it reverts to the default of disabled. 8.25. SLEEP This command is the only way to cause the drive to enter Sleep Mode. The drive is spun down, and when it is stopped, BSY is cleared, an interrupt is generated, and the interface becomes inactive. The only way to recover from Sleep Mode is with a software reset or a hardware reset. NOTE 12 The use of hardware reset to recover from Sleep Mode may be incompatible with continued operation of the host system. A drive shall not power on in Sleep Mode nor remain in Sleep Mode following a reset sequence. If the drive is already spun down, the spin down sequence is not executed. 8.26. STANDBY This command causes the drive to enter the Standby Mode. See 10.3 for protocol. The drive may return the interrupt before the transition to Standby Mode is completed. If the drive is already spun down, the spin down sequence is not executed. If the Sector Count register is non-zero then the automatic power down sequence shall be enabled and the timer shall begin counting down when the drive returns to Idle Mode. If the Sector Count register is zero then the automatic power down sequence shall be disabled. If the Sector Count register is non-zero then the Automatic Standby Mode sequence shall be enabled. The value in the Sector Count register shall be used to determine the Automatic Standby Mode Timeout period. If the Sector Count register is zero then the Automatic Standby Mode sequence shall be disabled. If the device is in the Idle Mode and the Automatic Standby Mode sequence is enabled, then the device shall begin an Automatic Standby Mode Timeout at the completion of any command or all tasks related to commands previously received. If the Automatic Standby Mode Timeout period elapses, the device shall enter the Standby Mode. The value in the Sector Count register when the STANDBY command is issued shall determine the period of the Automatic Standby Mode Timeout. The interpretation of the value in the Sector Count register is given in Table xx. (See Clause 8.11 for Table xx.) 8.27. STANDBY IMMEDIATE This command causes the drive to enter the Standby Mode. See 10.3 for protocol. The drive may return the interrupt before the transition to Standby Mode is completed. If the drive is already spun down, the spin down sequence is not executed. 8.28. WRITE BUFFER This command enables the host to overwrite the contents of the drive's sector buffer with any data pattern desired. See 10.2 for protocol. The READ BUFFER and WRITE BUFFER commands shall be synchronized within the drive such that sequential WRITE BUFFER and READ BUFFER commands access the same 512 bytes within the buffer. 8.29. WRITE DMA This command executes in a similar manner to WRITE SECTOR(S) except for the following: * the host initializes a slave-DMA channel prior to issuing the command * data transfers are qualified by DMARQ and are performed by the slave-DMA channel * the drive issues only one interrupt per command to indicate that data transfer has terminated and status is available. Any error encountered during WRITE DMA execution results in the termination of data transfer. The drive issues an interrupt to indicate that data transfer has terminated and status is available in the Error register. The error posting is the same as that of the WRITE SECTOR(S) command. 8.30. WRITE LONG This command is similar to the WRITE SECTOR(S) command except that it writes the data and the ECC bytes directly from the sector buffer; the drive does not generate the ECC bytes itself. Only single sector Write Long operations are supported. The transfer of the ECC bytes shall be one byte at a time over bits DD0-7 only (8- bits wide). 8.31. WRITE MULTIPLE command This command is similar to the WRITE SECTOR(S) command. The drive sets BSY within 400 nsec of accepting the command, and interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by SET MULTIPLE MODE. Command execution is identical to the WRITE SECTOR(S) operation except that the number of sectors defined by the SET MULTIPLE MODE command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the SET MULTIPLE MODE command, which shall be executed prior to the WRITE MULTIPLE command. When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = Remainder (SECTOR COUNT / block count) If the WRITE MULTIPLE command is attempted before the SET MULTIPLE MODE command has been executed or when WRITE MULTIPLE commands are disabled, the Write Multiple operation shall be rejected with an aborted command error. Disk errors encountered during WRITE MULTIPLE commands are posted after the attempted disk write of the block or partial block transferred. The Write command ends with the sector in error, even if it was in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. The contents of the Command Block Registers following the transfer of a data block which had a sector in error are undefined. The host should retry the transfer as individual requests to obtain valid error information. 8.32. WRITE SAME This command executes in a similar manner to WRITE SECTOR(S) except that only one sector of data is transferred. The contents of the sector are written to the medium one or more times. NOTE 13 The WRITE SAME command allows for initialization of part or all of the medium to the specified data with a single command. If the Features register is 22h, the drive shall write that part of the medium specified by the Sector Count, Sector Number, cylinder and Drive/Head registers. If the Features register contains DDh, the drive shall initialize all the user accessible medium. If the register contains a value other than 22h or DDh, the command shall be rejected with an aborted command error. The drive issues an interrupt to indicate that the command is complete. Any error encountered during execution results in the termination of the write operation. Status is available in the Error register if an error occurs. The error posting is the same as that of the WRITE SECTOR(S) command. 8.33. WRITE SECTOR(S) This command writes from 1 to 256 sectors as specified in the Sector Count register (a SECTOR COUNT of zero requests 256 sectors), beginning at the specified sector. See 10.1 for the DRQ, IRQ and BSY protocol on data transfers. If the drive is not already on the desired track, an implied seek is performed. Once at the desired track, the drive searches for the appropriate ID field. If retries are disabled and two index pulses have occurred without error free reading of the requested ID, an ID Not Found error is posted. If retries are enabled, up to a vendor specific number of attempts may be made to read the requested ID before posting an error. If the ID is read correctly, the data loaded in the buffer is written to the data field of the sector, followed by the ECC bytes. Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector written. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. 8.34. WRITE VERIFY This command is similar to the WRITE SECTOR(S) command, except that each sector is verified immediately after being written. The verify operation is a read without transfer and a check for data errors. Any errors encountered during the verify operation are posted. Multiple sector WRITE VERIFY commands write all the requested sectors and then verify all the requested sectors before generating the final interrupt. 9. Protocol Commands can be grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host first checks if BSY=1, and should proceed no further unless and until BSY=0. For most commands, the host will also wait for DRDY=1 before proceeding. Those commands shown with DRDY=x can be executed when DRDY=0. Data transfers may be accomplished in more ways than are described below, but these sequences should work with all known implementations of ATA drives. 9.1. PIO data in commands This class includes: * IDENTIFY DRIVE * READ BUFFER * READ LONG * READ SECTOR(S) Execution includes the transfer of one or more 512 byte (>512 bytes on READ LONG) sectors of data from the drive to the host. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Drive/Head registers. b) The host writes the command code to the Command register. c) The drive sets BSY and prepares for data transfer. d) When a sector of data is available, the drive sets DRQ and clears BSY prior to asserting INTRQ. e) After detecting INTRQ, the host reads the Status register, then reads one sector of data via the Data register. In response to the Status register being read, the drive negates INTRQ. f) The drive clears DRQ. If transfer of another sector is required, the drive also sets BSY and the above sequence is repeated from d). 9.1.1. PIO read command +- a) ---- b) -+ +- e) ----------+ +- e) ----------+ |Setup | Issue | | Read |Transfer| | Read |Transfer| | |command| |status| data |:::::::|status| data | |------+-------| |------+--------| |------+--------| |BSY=0 | |BSY=1 |BSY=0 | |BSY=1 |BSY=0 | | |DRDY=1 | | | | | | |DRQ=1 | |DRQ=0 |DRQ=1 | |DRQ=0 |Assert|Negate | |Assert|Negate INTRQ INTRQ INTRQ INTRQ If Error Status is presented, the drive is prepared to transfer data, and it is at the host's discretion that the data is transferred. 9.1.2. PIO Read aborted command +- a) ---- b) -+ +- e) -+ |Setup | Issue | | Read | | |command| |status| |------+-------| |------| |BSY=0 | |BSY=1 |BSY=0 | |DRDY=1 | | |DRQ=1 |DRQ=0 |Assert|Negate INTRQ INTRQ Although DRQ=1, there is no data to be transferred under this condition. 9.2. PIO data out commands This class includes: - Download Microcode - Format - WRITE BUFFER - WRITE LONG - WRITE SECTOR(S) Execution includes the transfer of one or more 512 byte (>512 bytes on WRITE LONG) sectors of data from the drive to the host. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Drive/Head registers. b) The host writes the command code to the Command register. c) The drive sets DRQ when it is ready to accept the first sector of data. d) The host writes one sector of data via the Data register. e) The drive clears DRQ and sets BSY. f) When the drive has completed processing of the sector, it clears BSY and asserts INTRQ. If transfer of another sector is required, the drive also sets DRQ. g) After detecting INTRQ, the host reads the Status register. h) The drive clears the interrupt. i) If transfer of another sector is required, the above sequence is repeated from d). 9.2.1. PIO write command +- a) ---- b) -+ +--------+ +- e) ----------+ +- e) -+ |Setup | Issue | |Transfer| | Read |Transfer| | Read | | |command| | data | |status| data |:::::::|status| |------+-------| |--------| |------+--------| |------| |BSY=0 | |BSY=1 |BSY=0 |BSY=1 |BSY=0 | |BSY=1 |BSY=0 | |DRDY=1 | | | | | | | |DRQ=1 |DRQ=0 |DRQ=1 | |DRQ=0 | | | | |Assert|Negate | |Assert|Negate INTRQ INTRQ INTRQ INTRQ 9.2.2. PIO write aborted command +- a) ---- b) -+ +- e) -+ |Setup | Issue | | Read | | |command| |status| |------+-------| |------| |BSY=0 | |BSY=1 |BSY=0 | |DRDY=1 | | | |Assert|Negate INTRQ INTRQ 9.3. Non-data commands This class includes: - EXECUTE DRIVE DIAGNOSTIC (DRDY=x) - IDLE - INITIALIZE DRIVE PARAMETERS (DRDY=x) - Read power mode - READ VERIFY SECTOR(S) - RECALIBRATE - SEEK - SET FEATURES - SET MULTIPLE MODE - STANDBY Execution of these commands involves no data transfer. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Drive/Head registers. b) The host writes the command code to the Command register. c) The drive sets BSY. d) When the drive has completed processing, it clears BSY and asserts INTRQ. e) The host reads the Status register. f) The drive negates INTRQ. 9.4. Miscellaneous commands This class includes: READ MULTIPLE SLEEP WRITE MULTIPLE WRITE SAME The protocol for these commands is contained in the individual command descriptions. 9.5. DMA data transfer commands (optional) This class comprises: READ DMA WRITE DMA Data transfers using DMA commands differ in two ways from PIO transfers: * data transfers are performed using the slave-DMA channel * no intermediate sector interrupts are issued on multi-sector commands Initiation of the DMA transfer commands is identical to the READ SECTOR(S) or WRITE SECTOR(S) commands except that the host initializes the slave-DMA channel prior to issuing the command. The interrupt handler for DMA transfers is different in that: * no intermediate sector interrupts are issued on multi-sector commands * the host resets the DMA channel prior to reading status from the drive. The DMA protocol allows high performance multi-tasking operating systems to eliminate processor overhead associated with PIO transfers. a) The Host initializes the slave-DMA channel b) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Drive/Head registers. c) The host writes the command code to the Command register. d) The drive sets DMARQ when it is ready to transfer any part the of data. e) The host transfers the data using the DMA transfer protocol currently in effect. f) When all of the data has been transferred, the drive generates an interrupt to the host g) Host resets the slave-DMA channel h) Host reads the Status register and, optionally, the Error register 9.5.1. Normal DMA transfer +----------------------+ +---------------------++----------------+ |Initialize DMA|Command| | DMA data transfer ||Reset DMA|Status| |----------------------| |---------------------+|---------+------+ |BSY=0 |BSY=1 |BSY=x |BSY=1 |BSY=0 |DRQ=x |nIEN=0 9.5.2. Aborted DMA transfer +----------------------+ +-------------+ +----------------+ |Initialize DMA|Command| | DMA data | |Reset DMA|Status| |----------------------| |-------------+ |---------+------+ |BSY=0 |BSY=1 |BSY=x |BSY=1 |BSY=0 |DRQ=1 |nIEN=0 9.5.3. Aborted DMA Command +----------------------+ +----------------+ |Initialize DMA|Command| |Reset DMA|Status| |----------------------| |---------+------+ |BSY=0 |BSY=1 |BSY=1 |BSY=0 |nIEN=0 10. Timing 10.1. Deskewing The host shall provide cable deskewing for all signals originating from the controller. The drive shall provide cable deskewing for all signals originating at the host. 10.2. Symbols Certain symbols are used in the timing diagrams. These symbols and their respective definitions are listed below. / or \ - signal transition (asserted or negated) * < or > - data transition (asserted or negated) XXXXXX - undefined but not necessarily released . . . - the "other" condition if a signal is shown with no change #n - used to number the sequence in which events occur e.g. #a, #b _ _ __ __/_ _/ - a degree of uncertainty as to when a signal may be asserted __ _ _ \_ _\__ - a degree of uncertainty as to when a signal may be negated * All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. 10.3. Terms The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted e.g. the following illustrates the representation of a signal named TEST going from negated to asserted and back to negated, based on the polarity of the signal. Assert Negate | | Bit Setting=1 |__________| Bit Setting=0 TEST _____/ \_______ Assert Negate | | Bit Setting=0 |__________| Bit Setting=1 TEST- _____/ \_______ 10.4. Data Transfers Figure 6 defines the relationships between the interface signals for both 16-bit and 8-bit data transfers. |<------------ t0 ------------------------>| _____ __________________________________________ | Address Valid *1 _____X \_________ |<-t1->| ->| t9 |<- | |<----------- t2 ------------>| |<-t8->| | |_____________________________|<---t2i---->|__ DIOR-/DIOW- ____________/ \____________/ | | | | | ____________ Write Data Valid *2------------------------------<____________>------------ | | |<--t3-->| | | | ->|t4|<- | | ____________ ____ Read Data Valid *2-------------------------------<____________X____>------ | | |<--t5-->| | | ->|t7|<- | | ->|t6 |<- | | | ->| tA |<- | ->|t6Z |<- | |__________________________________________ IOCS16- ________/ | | \______ | ->|tR|<- ________________|________________________________________ IORDY XXXXXXXXXXXXXXXXX___________________/ *1 Drive Address consists of signals CS0-, CS1- and DA2-0 *2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit) +----------------------------------------------------------------------+ | PIO |Mode 0|Mode 1|Mode 2|Mode 3| | timing parameters | nsec | nsec | nsec | nsec | +----+------------------------------------------+------+------+------+------+ | t0 | Cycle time (min) | 600 | 383 | 240 | 180 | | t1 | Address valid to DIOR-/DIOW- setup (min) | 70 | 50 | 30 | 30 | | t2 | DIOR-/DIOW- 16-bit (min) | 165 | 125 | 100 | 80 | | | Pulse width 8-bit (min) | 290 | 290 | 290 | 80 | | t2i| DIOR-/DIOW- recovery time (min) | | | | 70 | | t3 | DIOW- data setup (min) | 60 | 45 | 30 | 30 | | t4 | DIOW- data hold (min) | 30 | 20 | 15 | 10 | | t5 | DIOR- data setup (min) | 50 | 35 | 20 | 20 | | t6 | DIOR- data hold (min) | 5 | 5 | 5 | 5 | | t6Z| DIOR- data tristate (2) (max) | | | | 30 | | t7 | Addr valid to IOCS16- assertion (max) | 90 | 50 | 40 | 30 | | t8 | Addr valid to IOCS16- negation (max) | 60 | 45 | 30 | 30 | | t9 | DIOR-/DIOW- to address valid hold (min) | 20 | 15 | 10 | 10 | | tR | Read Data Valid to IORDY active (min) | | | | 0 | | | (if IORDY initially low after tA) | | | | | +---------------------------------------------------------------------------+ Figure 5 - PIO Data Transfer to/from Drive ___________________________________ DIOR-/DIOW- __________/ \______________ | |<- tA ->|<--- tB ---->| ___________________| |_____________________ IORDY \___________________/ +-------------------------------+-----+-----+-------+ | Description | Min | Max | Units | +-----+-------------------------------+-----+-----+-------+ | tA | IORDY Setup time | - | 35| nsecs | | tB | IORDY Pulse Width | - |1,250| nsecs | +-----+-------------------------------+-----+-----+-------+ WARNING: The use of IORDY for data transfers is a system integration issue which requires control of both ends of the cable. Figure 6 - IORDY Timing Requirements |<----------------------- t0 ----------------------->| ____________ _______ DMARQ ___/ \_______________________________________/ | |<- tC ->| | |______________________________________________ |___ DMACK- _______/ \_____/ |<--- tI --->|_________________|<----- tJ -----| | DIOR-/DIOW- ____________________/ \_________________________ | | | | | |<------ tD ----->| | Read | _________________ | DD0-15 -----------------------------<_________________>---------------- | |<- tE ->|<- tS ->|<- tF ->| | Write | __________________________ | DD0-15 --------------------------<__________________________>----------- | | | | | | |<--- tG --->|<-- tH -->| | +----------------------------------------------------------+ | Single word DMA | Mode 0| Mode 1| Mode 2| | timing parameters | nsec | nsec | nsec | +----+----------------------------------+-------+-------+-------| | t0 | Cycle time (min) | 960 | 480 | 240 | | tC | DMACK to DMREQ delay (max) | 200 | 100 | 80 | | tD | DIOR-/DIOW- 16-bit (min) | 480 | 240 | 120 | | tE | DIOR- data access (max) | 250 | 150 | 60 | | tF | DIOR- data hold (min) | 5 | 5 | 5 | | tG | DIOW- data setup (min) | 250 | 100 | 35 | | tH | DIOW- data hold (min) | 50 | 30 | 20 | | tI | DMACK to DIOR-/DIOW- setup (min) | 0 | 0 | 0 | | tJ | DIOR-/DIOW- to DMACK hold (min) | 0 | 0 | 0 | | tS | DIOR- setup (min) | tD-tE | tD-tE | tD-tE | +---------------------------------------------------------------+ Figure 7 - Single Word DMA Data Transfer |<------------- t0 ------------>| _____________________________________________ _ _ _ _ _ ________ DMARQ ___/ \__________/ | |<--->| | | tL ___________________________________________________ _ DMACK- ______/ \________/ |<-->| | | | tI |<-- tD ->|<------- tK -------->| |<-->| | | | | tJ | DIOR- |_________| |_________ | DIOW- ___________/ \_____________________/ \_______________ | | | |<--->| | -->| |<-tZ READ tE ________ _ _ _ _ _ _ _ _ _ _ _ ___________ DD0-15 -----------------<________X_X_X_X_X_X_X_X_X_X_X_X<_______X_X_>------- | | |<-->| | tF WRITE ____________ _ _ _ _ _ _ _ _ _ ____________ DD0-15 --------------<____________XX_X_X_X_X_X_X_X_X_X____________>--------- |<---->|<--->| tG tH +----------------------------------------+-----------+ | Multiword DMA | Mode 0 | Mode 1 | | timing parameters | nsec | nsec | | | Min | Max | Min | Max | +-----+----------------------------+-----+-----|-----+-----| | t0 | Cycle time | 480 | | 150 | | | tC | DMACK to DMREQ delay | | --- | | --- | | tD | DIOR-/DIOW- 16-bit | 215 | | 80 | | | tE | DIOR- data access | | 150 | | 60 | | tF | DIOR- data hold | 5 | | 5 | | | tFZ | DIOR- to tristate (1) | | 20 | | 25 | | tG | DIOW- data setup | 100 | | 30 | | | tH | DIOW- data hold | 20 | | 15 | | | tI | DMACK to DIOR-/DIOW- setup | 0 | | 0 | | | tJ | DIOR-/DIOW- to DMACK hold | 20 | | 5 | | | tKr | DIOR- negated pulse width | 50 | | 50 | | | tKw | DIOW- negated pulse width | 215 | | 50 | | | tLr | DIOR- to DMREQ delay | | 120 | | 40 | | tLw | DIOW- to DMREQ delay | | 40 | | 40 | +----------------------------------------------+-----------+ (1) Meaning of this parameter in the original ATA standard is not clear. This parameter has been renamed to tFZ and specifies the time from the negation edge of DMACK- to the time that the data bus is no longer driven by the device (tristate). The tZ parameter applies only at the end of a Multiword DMA cycle, i.e., when DMACK is negated. The device should actively drive the data bus, or may tristate the data bus, while DMACK- is active from the first time that DIOR- is asserted until DMACK- is deasserted as long as tE and tF requirements are met. Figure 8 - Multiword DMA Data Transfer 10.5. Power on and hard reset ______ RESET- _____/ \_____________________________________________________ |<-tM->| | | | | | | Drive 0 _ _ _ _ _ _ _ _______ _ _ _ _ _ _ _ _ _ _ _ _ _| BSY _ _ _ _ _ _ _/ \_ _ _ _ _ *1 _ _ _ _ _ _\________________ ->|tN|<- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DASP- _ _ _ _ _ _ _ _\_______/_ _ _ _ *2 _ _ _ _ _ _ _ _ _ _\=== *3 == ->| tP |<- | |_ _ _ __________ Control Registers_______________________________________/_ _ _ / | | | | | | | | Drive 1 _ _ _ _ _ _ _ _ _________________________________| BSY _ _ _ _ _ _ _ _/ \________________ _ _ _ _ _ _ _ _ _ _ ______ _ _ _ _ _ PDIAG- _ _ _ _ _ _ _ _ _ _\____________________________/ \_ _ _ _ _ | |<----------- tQ -------->| _ _ _ _ _ _ _ _ _ _ _ _ _________________________ _ _ _ DASP- _ _ _ _ _ _ _ _ _ _ _ _/ \ _ _ _\=== *3 == |<- tR ->| |<-------------------- tS ----------------->| _ _ _ __________ Control Registers_______________________________________/_ _ _ / *1 Drive 0 can set BSY=0 if Drive 1 not present *2 Drive 0 can use DASP- to indicate it is active if Drive 1 is not present *3 DASP- can be asserted to indicate that the drive is active +--------------------------------+ | Label | Units | |-------------------+------------| | tM (Min) | 25 usec | | tN (Max) | 400 nsec | | tP (Max) | 1 msec | | tQ (Max) | 30 secs | | tR Drive 0 (Max) | 450 msec | | tR Drive 1 (Max) | 400 msec | | tS (Max) | 31 secs | +--------------------------------+ Figure 9 - Reset Sequence Annex A. Diagnostic and reset considerations (informative) This annex describes the following timing relationships during: a) Power on and hardware resets - One drive - Two drives b) Software reset - One drive - Two drives c) Diagnostic command execution - One drive - Two drives - Two drives - drive 1 failed The diagnostic and reset architecture requires the following: * DASP- is asserted by Drive 1 and received by Drive 0 at power-on or hardware reset to indicate the presence of Drive 1. At all other times it is asserted by Drive 0 and Drive 1 to indicate when a drive is active. * PDIAG- is asserted by Drive 1 and detected by Drive 0. It is used by Drive 1 to indicate to Drive 0 that it has completed diagnostics and is ready to accept commands from the Host (BSY bit is cleared). This does not indicate that the drive is ready, only that it can accept commands. This line may remain asserted until the next reset occurs or an Execute Diagnostic command is received. * Unless indicated otherwise, all times are relative to the event that triggers the operation (RESET-, SRST=1, Execute Diagnostic Command). A.1. Power on and hardware resets A.1.1. Power on and hardware resets - one drive * Host asserts RESET- for a minimum of 25 usec. * Drive 0 sets BSY within 400 nsecs after RESET- is negated. * Drive 0 negates DASP- within 1 msec after RESET- is negated. * Drive 0 performs hardware initialization * Drive 0 may revert to its default condition * Drive 0 waits 1 msec then samples for at least 450 msec for DASP- to be asserted from Drive 1. * Drive 0 clears BSY when ready to accept commands (within 31 seconds). A.1.2. Power on and hardware resets - two drives * Host asserts RESET- for a minimum of 25 usec. * Drive 0 and Drive 1 set BSY within 400 nsec after RESET- negated. * DASP- is negated within 1 msec after RESET- is negated. A.1.2.1. Drive 1 * Drive 1 negates PDIAG- before asserting DASP-. * Drive 1 asserts DASP- within 400 msecs after RESET- (to show presence). * Drive 1 performs hardware initialization and executes its internal diagnostics. * Drive 1 may revert to its default condition * Drive 1 posts diagnostic results to the Error register * Drive 1 clears BSY when ready to accept commands. * Drive 1 asserts PDIAG- to indicate that it is ready to accept commands (within 30 seconds from RESET-). * Drive 1 negates DASP- after the first command is received or negates DASP- if no command is received within 31 seconds after RESET-. A.1.2.2. Drive 0 * Drive 0 performs hardware initialization and executes its internal diagnostics. * Drive 0 may revert to its default condition * Drive 0 posts diagnostic results to the Error register * After 1 msec, Drive 0 waits at least 450 msec for DASP- to be asserted (from Drive 1). If DASP- is not asserted, no Drive 1 is present (see Power-on reset - One Drive operation). * Drive 0 waits up to 31 seconds for Drive 1 to assert PDIAG-. If PDIAG- is not asserted, Drive 0 sets Bit 7=1 in the Error register. * Drive 0 clears BSY when ready to accept commands (within 31 seconds). A.2. Software reset A.2.1. Software reset - one drive * Host sets SRST=1 in the Device Control register. * Drive 0 sets BSY within 400 nsec after detecting that SRST=1. * Drive 0 performs hardware initialization and executes its internal diagnostics. * Drive 0 may revert to its default condition. * Drive 0 posts diagnostic results to the Error register. * Drive 0 clears BSY when ready to accept commands (within 31 seconds). A.2.2. Software reset - two drives * Host sets SRST=1 in the Device Control register. * Drive 0 and Drive 1 set BSY within 400 nsec after detecting that SRST=1. * Drive 0 and Drive 1 perform hardware initialization. * Drive 0 and Drive 1 may revert to their default condition. A.2.2.1. Drive 1 * Drive 1 negates PDIAG- within 1 msec. * Drive 1 clears BSY when ready to accept commands. * Drive 1 asserts PDIAG- to indicate that it is ready to accept commands (within 30 seconds). A.2.2.2. Drive 0 * Drive 0 waits up to 31 seconds for Drive 1 to assert PDIAG-. * Drive 0 clears BSY when ready to accept commands (within 31 seconds). A.3. Diagnostic Command Execution A.3.1. Diagnostic command execution - one drive (passed) * Drive 0 sets BSY within 400 nsec after the Execute Diagnostic command was received. * Drive 0 performs hardware initialization and internal diagnostics. * Drive 0 resets Command Block registers to default condition. * Drive 0 posts diagnostic results to the Error register * Drive 0 clears BSY when ready to accept commands (within 6 seconds). A.3.2. Diagnostic command - two drives (passed) * Drive 0 and Drive 1 set BSY within 400 nsec after the Execute Diagnostic command was received. A.3.2.1. Drive 1 * Drive 1 negates PDIAG- within 1 msec after command received. * Drive 1 performs hardware initialization and internal diagnostics. * Drive 1 resets the Command Block registers to their default condition. * Drive 1 posts diagnostic results to the Error register * Drive 1 clears BSY when ready to accept commands. * Drive 1 asserts PDIAG- to indicate that it is ready to accept commands (within 5 seconds). A.3.2.2. Drive 0 * Drive 0 performs hardware initialization and internal diagnostics. * Drive 0 resets the Command Block registers to their default condition. * Drive 0 waits up to 6 seconds for Drive 1 to assert PDIAG-. * Drive 0 posts diagnostic results to the Error register * Drive 0 clears BSY when ready to accept commands (within 6 seconds). A.3.3. Diagnostic command execution - one drive (failed) * Drive 0 sets BSY within 400 nsec after Diagnostic command received. * Drive 0 performs hardware initialization and internal diagnostics. * Drive 0 resets Command Block registers to default condition. * Drive 0 posts a Diagnostic Code to the Error register indicating a failure. * Drive 0 clears BSY when ready to accept commands (within 6 seconds) A.3.4. Diagnostic command execution - two drives (drive 1 failed) * Drive 0 and Drive 1 set BSY within 400 nsec after Diagnostic command received. A.3.4.1. Drive 1 * Drive 1 negates PDIAG- within 1 msec after command received. * Drive 1 performs hardware initialization and internal diagnostics. * Drive 1 resets the Command Block registers to their default condition. * Drive 1 posts a Diagnostic Code to the Error register indicating failure. * Drive 1 clears BSY. * Drive 1 does not assert PDIAG-, indicating that it failed diagnostics. A.3.4.2. Drive 0 * Drive 0 performs hardware initialization and internal diagnostics. * Drive 0 resets the Command Block registers to their default condition. * Drive 0 waits 6 seconds for Drive 1 to assert PDIAG- but PDIAG- is not asserted by Drive 1. * Drive 0 posts a Diagnostic Code to the Error register setting Bit 7=1 to indicate that Drive 1 failed diagnostics. * Drive 0 clears BSY when ready to accept commands (within 6 seconds). NOTE 1 The 6 seconds referenced above is a host-oriented value. Annex B. Diagnostic and reset considerations (informative) B.1. Power on and hardware reset (RESET-) DASP- is read by Drive 0 to determine if Drive 1 is present. If Drive 1 is present Drive 0 will read PDIAG- to determine when it is valid to clear BSY and whether Drive 1 has powered on or reset without error, otherwise Drive 0 clears BSY whenever it is ready to accept commands. Drive 0 may assert DASP- to indicate drive activity. B.2. Software reset If Drive 1 is present Drive 0 will read PDIAG- to determine when it is valid to clear BSY and whether Drive 1 has reset without any errors, otherwise Drive 0 will simply reset and clear BSY. DASP- is asserted by Drive 0 (and Drive 1 if it is present) in order to indicate drive active. B.3. Drive diagnostic command If Drive 1 is present, Drive 0 will read PDIAG- to determine when it is valid to clear BSY and if Drive 1 passed or failed the EXECUTE DRIVE DIAGNOSTIC command, otherwise Drive 0 will simply execute its diagnostics and then clear BSY. DASP- is asserted by Drive 0 (and Drive 1 if it is present) in order to indicate the drive is active. B.4. Truth table In all the above cases: Power on, RESET-, software reset, and the EXECUTE DRIVE DIAGNOSTIC command the Drive 0 Error register is calculated as follows: +-----------+------------+-----------+-----------+ | Drive 1 | PDIAG- | Drive 0 | Error | | Present? | Asserted? | Passed | Register | +-----------+------------+-----------+-----------+ | Yes | Yes | Yes | 01h | | Yes | Yes | No | 0xh | | Yes | No | Yes | 81h | | Yes | No | No | 8xh | | No | (not read) | Yes | 01h | | No | (not read) | No | 0xh | +-----------+------------+-----------+-----------+ Where x indicates the appropriate Diagnostic Code for the Power on, RESET-, software reset, or drive diagnostics error. Table 15 - Reset Error register Values B.5. Power on or hardware reset algorithm 1) Power on or hardware reset 2) The hardware should automatically do the following: a) Set up the hardware to post both Drive 0 and Drive 1 status b) Set the Drive 0 Status register to 80h (set BSY and clear all the other status bits) c) Set the Drive 1 Status register to 80h (set BSY and clear all the other status bits) 3) Determine whether the device is Drive 0 or Drive 1 4) Perform any remaining time critical hardware initialization including starting the spin up of the disk if needed 5) If Drive 1 a) Negate the PDIAG- signal b) Set up PDIAG- as an output c) Assert the DASP- output d) Set up DASP- as an output if necessary e) Set up the hardware so it posts Drive 1 status only and continue to post 80h for Drive 1 status NOTE 2 all this must happen within 400 msec after power on or RESET- If Drive 0 a) Set up PDIAG- as an input b) Release DASP- and set up DASP- as an input c) Test DASP- for 450 msec or until DASP- is asserted by Drive 1 d) If DASP- is asserted within 450 msec i) note that Drive 1 is present ii) set up the hardware so it posts Drive 0 status only and continue to post 80h for the Drive 0 status If DASP- is not asserted within 450 msec i) note that Drive 1 is not present e) Assert DASP- to indicate drive activity 6) Complete all the hardware initialization needed to get the drive ready, including: a) Set the Sector Count register to 01h b) Set the Sector Number register to 01h c) Set the Cylinder Low register to 00h d) Set the Cylinder High register to 00h e) Set the Drive/Head register to 00h 7) If Drive 1 and power on, or RESET- is valid a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 Status register to 00h c) Assert PDIAG- NOTE 3 All this must happen within 30 seconds of power on or the negation of RESET- If Drive 1 and power on or RESET- bad a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 Status register to 00h NOTE 4 All this must happen within 30 seconds of power on or the negation of RESET- If Drive 0, power on or RESET- valid, and a Drive 1 is present a) Test PDIAG- for 31 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 31 seconds i) Set the Error register to Diagnostic Code 01h c) If PDIAG- is not asserted within 31 seconds i) Set the Error register to 81h d) Set the Drive 0 Status register to 00h If Drive 0, power on or RESET- bad, and a Drive 1 is present a) Test PDIAG- for 31 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 31 seconds i) Set the Error register to the appropriate Diagnostic Code c) If PDIAG- is not asserted within 31 seconds i)Set the Error register to 80h + the appropriate code d) Set the Drive 0 Status register to 00h If Drive 0, power on or RESET- valid, and no Drive 1 is present a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 00h If Drive 0, power on or RESET- bad, and no Drive 1 is present a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 00h 8) Finish spin up if needed 9) If Drive 1 a) Set the Drive 1 Status register to 50h b) Negate DASP- if a command is not received within 31 seconds If Drive 0 and a Drive 1 is present a) Set the Drive 0 Status register to 50h b) Negate DASP- If Drive 0 and no Drive 1 is present a) Leave the Drive 1 Status register 00h b) Set the Drive 0 Status register to 50h c) Negate DASP- B.6 Software Reset Algorithm 1) The software reset bit is set 2) If Drive 1 a) The hardware should set BUSY in the Drive 1 Status register b) Negate the PDIAG- signal NOTE 5 this must happen within 1 msec of the software reset If Drive 0 and Drive 1 is present a) The hardware should set BUSY in the Drive 0 Status register If Drive 0 and there is no Drive 1 the hardware should: a) Set BUSY in the Drive 0 Status register b) Set the Drive 1 Status register to 80h 3) Assert DASP- 4) Finish all the hardware initialization needed to place the drive in reset 5) Wait for the software reset bit to clear 6) Finish all hardware initialization needed to get the drive ready to receive any type of command from the host including: a) Set the Sector Count register to 01h b) Set the Sector Number register to 01h c) Set the Cylinder Low register to 00h d) Set the Cylinder High register to 00h e) Set the Drive/Head register to 00h If Drive 1 and reset valid a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 Status register to 50h c) Assert PDIAG- NOTE 6 All this must happen within 30 seconds of the clearing of the software reset bit If Drive 1 and reset bad a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 Status register to 50h NOTE 7 All this must happen within 30 seconds of the clearing of the software reset bit If Drive 0, reset valid, and a Drive 1 is present a) Test PDIAG- for 31 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 31 seconds i) Set the Error register to Diagnostic Code 01h c) If PDIAG- is not asserted within 31 seconds i) Set the Error register to 81h d) Set the Drive 0 Status register to 50h If Drive 0, reset bad, and a Drive 1 is present a) Test PDIAG- for 31 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 31 seconds i) Set the Error register to the appropriate Diagnostic Code c) If PDIAG- is not asserted within 31 seconds i) Set the Error register to 80h + the appropriate code d) Set the Drive 0 Status register to 50h If Drive 0, reset valid, and no Drive 1 is present a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 50h If Drive 0, reset bad, and no Drive 1 is present a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 50h B.7. Diagnostic Command Algorithm 1) The diagnostics command is received 2) If Drive 1 a) The hardware should set BUSY in the Drive 1 Status register b) Negate the PDIAG- signal NOTE 8 this must happen within 1 msec after command acceptance If Drive 0 and Drive 1 is present a) The hardware should set BUSY in the Drive 0 Status register If Drive 0 and there is no Drive 1 the hardware should a) Set BUSY in the Drive 0 Status register b) Set BUSY in the Drive 1 Status register 3) Assert DASP- 4) Perform all the drive diagnostics and note their results 5) Finish all the hardware initialization needed to get the drive ready to receive any type of command from the host including: a) Set the Sector Count register to 01h b) Set the Sector Number register to 01h c) Set the Cylinder Low register to 00h d) Set the Cylinder High register to 00h e) Set the Drive/Head register to 00h 6) If Drive 1 and passed a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 status to 50h c) Assert PDIAG- NOTE 9 All this must happen within 5 seconds of the acceptance of the diagnostic command If Drive 1 and did not pass a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 status to 50h NOTE 10 All this must happen within 5 seconds of the acceptance of the diagnostic command If Drive 0, passed, and a Drive 1 is present a) Test PDIAG- for 6 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 6 seconds i) Set the Error register to Diagnostic Code 01h c) If PDIAG- is not asserted within 6 seconds i) Set the Error register to 81h d) Set the Drive 0 status to 50h e) Issue interrupt to the host If Drive 0, did not pass, and a Drive 1 is present a) Test PDIAG- for 6 seconds or until PDIAG- is asserted by Drive 1 b) If PDIAG- is asserted within 6 seconds i) Set the Error register to the appropriate Diagnostic Code c) If PDIAG- is not asserted within 6 seconds i) Set the Error register to 80h + the appropriate code d) Set the Drive 0 Status register to 50h e) Issue interrupt to the host If Drive 0, passed, and no Drive 1 is present a) Set the Error register to Diagnostic Code 01h b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 50h d) Issue interrupt to the host If Drive 0, did not pass, and no Drive 1 is present a) Set the Error register to the appropriate Diagnostic Code b) Set the Drive 1 Status register to 00h c) Set the Drive 0 Status register to 50h d) Issue interrupt to the host Annex C. 44-Pin Small Form Factor Connector (informative) This annex describes the connector-connector mating alternatives for 2 1/2" disk drives or smaller which were developed by the Small Form Factor (SFF) Committee, an industry ad hoc group. In an effort to broaden the applications for small form factor disk drives, a group of companies representing system integrators, peripheral suppliers, and component suppliers decided to address the issues involved. A primary purpose of the SFF Committee was to define the external dimensions of small form factor disk drives so that products from different vendors could be used in the same mounting configurations. The restricted area, and the mating of drives directly to a motherboard required that the number of connectors be reduced, which caused the assignment of additional pins for power. Power is provided to the drives on the same connector as used for the signals, and addresses are set by the receptacle into which the drives are plugged. The 50-pin connector that has been widely adopted across industry for SFF drives is a low density 2mm connector which has no shroud on the plug which is mounted on the drive. A number of suppliers provide intermatable components. The following information has been provided to assist users in specifying components used in an implementation. Signals Connector Plug DuPont 86451 or equivalent Signals Connector Receptacle DuPont 86455 or equivalent C.1. 44-pin signal assignments The signals assigned for 44-pin applications are described in table 13. Although there are 50 pins in the plug, the mating receptacle need contain only 44 pins (the removal of pins E and F provides room for the wall of the receptacle). 44-pin signal assignments for ATA The first four pins of the connector plug located on the drive are not to be connected to the host, as they are reserved for manufacturer's use. Pins E, F and 20 are keys, and are removed. +-------------------------------------------1-E-----+ | o o o o o o o o o o o o o o o o o o o o o o K C A | | o o o o o o o o o o o o K o o o o o o o o o K D B | +44----------------------20-----------------2-F-----+ +=================-=========-=============-=========-==================+ | Signal |Connector| |Connector| Signal | | name | contact | Conductor | contact | name | |-----------------+---------+-------------+---------+------------------| | Vendor unique | A | | B | Vendor unique | | Vendor unique | C | | D | Vendor unique | | (keypin) | E | | F | (keypin) | | RESET- | 1 | 1 | 2 | 2 | Ground | | DD7 | 3 | 3 | 4 | 4 | DD8 | | DD6 | 5 | 5 | 6 | 6 | DD9 | | DD5 | 7 | 7 | 8 | 8 | DD10 | | DD4 | 9 | 9 | 10 | 10 | DD11 | | DD3 | 11 | 11 | 12 | 12 | DD12 | | DD2 | 13 | 13 | 14 | 14 | DD13 | | DD1 | 15 | 15 | 16 | 16 | DD14 | | DD0 | 17 | 17 | 18 | 18 | DD15 | | Ground | 19 | 19 | 20 | 20 | (keypin) | | DMARQ | 21 | 21 | 22 | 22 | Ground | | DIOW- | 23 | 23 | 24 | 24 | Ground | | DIOR- | 25 | 25 | 26 | 26 | Ground | | IORDY | 27 | 27 | 28 | 28 | PSYNC:CSEL | | DMACK- | 29 | 29 | 30 | 30 | Ground | | INTRQ | 31 | 31 | 32 | 32 | IOCS16- | | DA1 | 33 | 33 | 34 | 34 | PDIAG- | | DAO | 35 | 35 | 36 | 36 | DA2 | | CS0- | 37 | 37 | 38 | 38 | CS1- | | DASP- | 39 | 39 | 40 | 40 | Ground | |* +5v (Logic) | 41 | 41 | 42 | 42 | +5V (Motor) * | |* Ground (Return)| 43 | 43 | 44 | 44 | TYPE- (0=ATA)* | |----------------------------------------------------------------------| | * Pins which are additional to those of the 40-pin cable. | +======================================================================+ Table 16 - Signal Assignments for 44-Pin ATA Annex D. 68-Pin Small Form Factor Connector (informative) D.1. Overview This appendix defines the pinouts used for the 68-pin alternative connector for the AT Attachment Interface. This connector is the same as the one defined by PCMCIA. This appendix defines a pinout alternative that allows a device to function as an AT Attachment Interface compliant device, while also allowing the device to be compliant with PC Card-ATA mode defined by PCMCIA. The signal protocol allows the device to identify the host interface as being 68-pin ATA or PCMCIA. To simplify the implementation of dual-interface devices, the 68-pin AT Attachment Interface maintains commonality with as many PC Card-ATA signals as possible, while supporting full command and signal compliance with the ATA standard. The 68-pin ATA pinout does not cause damage or loss of data if a PCMCIA card is accidentally plugged into a host slot supporting this interface. The inversion of the reset signal between the ATA and PCMCIA interfaces prevents loss of data if the device is unable to reconfigure itself to the appropriate host interface. D.2. Signals This Specification relies upon the electrical and mechanical characteristics of PCMCIA and unless otherwise noted, all signals and registers with the same names as PCMCIA signals and registers have the same meaning as defined in PCMCIA. The PC Card-ATA specification is used as a reference to identify the signal protocol used to identify the host interface protocol. Unless otherwise noted, all signals and registers with the same names as ATA signals and registers have the same meaning as defined in X3.221-199x, which defines the protocol by which commands are directed to the storage device. D.4. Signal Descriptions Any signals not defined below are as described in the ATA, PCMCIA, or the PC Card- ATA documents. Table X-1 shows the ATA signals and relationships such as direction, as well as providing the signal name of the PCMCIA equivalent. ====================================== ==================================== |Pin | Signal |Hst|Dir|Dev| PCMCIA | |Pin | Signal |Hst|Dir|Dev| PCMCIA | ====================================== ==================================== | 1 | Ground | x ---> x | Ground | | 35 | Ground | x ---> x | Ground | | 2 | DD3 | x <---> x | D3 | | 36 | CD1- | x <--- x | CD1- | | 3 | DD4 | x <---> x | D4 | | 37 | DD11 | x <---> x | D11 | | 4 | DD5 | x <---> x | D5 | | 38 | DD12 | x <---> x | D12 | | 5 | DD6 | x <---> x | D6 | | 39 | DD13 | x <---> x | D13 | | 6 | DD7 | x <---> x | D7 | | 40 | DD14 | x <---> x | D14 | | 7 | CS0- | x ---> x | CE1- | | 41 | DD15 | x <---> x | D15 | | 8 | | ---> i | A10 | | 42 | CS1- | x --->x*1| CE2- | | 9 | SELATA-| x ---> x | OE- | | 43 | | ---> i | Refresh| | 10 | | | | | 44 | DIOR- | x ---> x | IORD- | | 11 | CS1- | x --->x*1| A9 | | 45 | DIOW- | x ---> x | IOWR- | | 12 | | ---> i | A8 | | 46 | | | | | 13 | | | | | 47 | | | | | 14 | | | | | 48 | | | | | 15 | | ---> i | WE- | | 49 | | | | | 16 | INTRQ | x <--- x | R/B/IREQ-| | 50 | | | | | 17 | VCC | x ---> x | VCC | | 51 | VCC | x ---> x | VCC | | 18 | | | | | 52 | | | | | 19 | | | | | 53 | | | | | 20 | | | | | 54 | | | | | 21 | | | | | 55 | M/S- | x --->x*2| | | 22 | | ---> i | A7 | | 56 | CSEL | x --->x*2| | | 23 | | ---> i | A6 | | 57 | | <--- i | RFU | | 24 | | ---> i | A5 | | 58 | RESET- | x ---> x | RESET | | 25 | | ---> i | A4 | | 59 | IORDY | o <--- x*3| WAIT- | | 26 | | ---> i | A3 | | 60 | DMARQ | o <--- x*3| INPACK-| | 27 | DA2 | x ---> x | A2 | | 61 | DMACK- | o ---> o | REG- | | 28 | DA1 | x ---> x | A1 | | 62 | DASP- | x <---> x | SPKR- | | 29 | DA0 | x ---> x | A0 | | 63 | PDIAG- | x <---> x | STSCHG-| | 30 | DD0 | x <---> x | D0 | | 64 | DD8 | x <---> x | D8 | | 31 | DD1 | x <---> x | D1 | | 65 | DD9 | x <---> x | D9 | | 32 | DD2 | x <---> x | D2 | | 66 | DD10 | x <---> x | D10 | | 33 | IOCS16-| x <--- x | IOIS16- | | 67 | CD2- | x <--- x | CD2- | | 34 | Ground | x ---> x | Ground | | 68 | Ground | x ---> x | Ground | ====================================== ==================================== Table 17 - Signal Assignments for 68-Pin ATA The Dir column indicates the direction of the signal between host and device. An x in the Hst column means this signal shall be supported by the Host. An x in the Dev column means this signal shall be supported by the device. An i in the Dev column means this signal shall be ignored by the device while in 68-pin ATA mode. An o means this signal is Optional. If there is nothing in Dev column for a pin location, then no connection should be made to that pin. NOTES: *1 The device shall support only one CS1- signal pin. *2 The device shall support either M/S- or CSEL but not both. *3 The device shall hold this signal negated if it does not support the function. D.4.1. CD1- (Card Detect 1) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. D.4.2. CD2- (Card Detect 2) This signal shall be grounded by the device. CD1- and CD2- are used by the host to detect the presence of the device. D.4.3. CS1- (Drive chip Select 1) Hosts shall provide CS1- on both the pins identified in Table 6-1. Devices are required to recognize only one of the two pins as CS1-. D.4.4. DMACK- (DMA Acknowledge) This signal is optional for hosts. This signal is optional for devices. If this signal is supported by the host or the device, the function of DMARQ shall also be supported. D.4.5. DMARQ (DMA Request) This signal is optional for hosts. Devices shall hold this signal negated if the function is not implemented. If this signal is supported by the host or the device, the function of DMACK- shall also be supported. D.4.6. IORDY (I/O Channel Ready) This signal is optional for hosts. Devices shall hold this signal negated if the function is not implemented. D.4.7. M/S- (Master/Slave) This signal is the inverted form of CSEL. Hosts shall support both M/S- and CSEL though devices need only support one or the other. Hosts shall assert CSEL and M/S- prior to applying VCC to the connector. D.4.8. SELATA- (Select 68-pin ATA) This pin is used by the host to select which mode to use, PC Card-ATA mode or the 68-pin ATA mode. To select 68-pin ATA mode, the host shall assert SELATA- prior to applying power to the connector, and shall hold SELATA- asserted. The device shall not re-sample SELATA- as a result of either a Hard or Soft Reset. The device shall ignore all interface signals for 19 msec after the host supplies Vcc within the device's voltage tolerance. If SELATA- is negated following this time, the device shall either configure itself for PC Card-ATA mode or not respond to further inputs from the host. D.5. Removability Considerations This Specification supports the removability of devices which use the ATA protocol. As removability is a new consideration for ATA devices, several issues need to be considered with regard to the insertion or removal of devices. D.5.1. Device Recommendations The following are recommendations to device implementors: * CS0-, CS1-, RESET- and SELATA- should be negated on the device to prevent false selection during hot insertion. * Ignore all interface signals except SELATA- until 19 msec after the host supplies VCC within the device's voltage tolerance. This time is necessary to de-bounce the device's power on reset sequence. Once in the 68-pin ATA mode, if SELATA- is ever negated following the 19 msec de-bounce delay time, the device should disable itself until VCC is removed. * The DOOR LOCK and DOOR UNLOCK commands should be used as per X3.221. D.5.2. Host Recommendations The following are recommendations to host implementors: * Connector pin sequencing should protect the device by making contact to ground before any other signal in the system. * SELATA- should be asserted at all times. * All devices should be reset and reconfigured to the same base address each time a device at that address is inserted or removed. * The removal or insertion of a device at the same address should be detected so as to prevent the corruption of a command. * The DOOR LOCK and DOOR UNLOCK commands should be used as per X3.221. Annex E. ATA Command Set Summary (informative) The following two tables are provided to facilitate the understanding of the ATA command set. Table 15 provide information on which command codes are currently defined. Table 16 provides a list of all of the ATA commands in order of command code. +------------+------------+------------+------------+ | x0 x1 x2 x3| x4 x5 x6 x7| x8 x9 xA xB| xC xD xE xF| +----+------------+------------+------------+------------+ | 0x | C R R R | R R R R | R R R R | R R R R | | 1x | C * * * | * * * * | * * * * | * * * * | | 2x | C C C C | R R R R | R R R R | R R R R | | 3x | C C C C | R R R R | R R R R | C R R R | +----+------------+------------+------------+------------+ | 4x | C C R R | R R R R | R R R R | R R R R | | 5x | C R R R | R R R R | R R R R | R R R R | | 6x | R R R R | R R R R | R R R R | R R R R | | 7x | C * * * | * * * * | * * * * | * * * * | +----+------------+------------+------------+------------+ | 8x | V V V V | V V V V | V V V V | V V V V | | 9x | C C C R | C C C C | C C V R | R R R R | | Ax | R R R R | R R R R | R R R R | R R R R | | Bx | R R R R | R R R R | R R R R | R R R R | +----+------------+------------+------------+------------+ | Cx | V V V V | C C C R | C C C C | R R R R | | Dx | R R R R | R R R R | R R R C | C C C C | | Ex | C C C C | C C C R | C C R R | C R R C | | Fx | V V V V | V V V V | V V V V | V V V V | +----+------------+------------+------------+------------+ Notes: * - Values 11h through 1Fh are identical to command 10h Values 71h through 7Fh are identical to command 70h C - a unique command R - Reserved, undefined in current specifications V - Vender Unique commands Table 18 - Command Matrix +------------------------------------+--------------+ | Command Name | Command Code | +------------------------------------+--------------+ | NOP | 00h | | Reserved | 01h-0Fh | | RECALIBRATE | 1xh | | READ SECTOR(S) (w/retry) | 20 | | READ SECTOR(S) (w/o retry) | 21 | | READ LONG (w/retry) | 22 | | READ LONG (w/o retry) | 23 | | Reserved | 24h-2Fh | | WRITE SECTOR(S) (w/retry) | 30 | | WRITE SECTOR(S) (w/o retry) | 31 | | WRITE LONG (w/retry) | 32 | | WRITE LONG (w/o retry) | 33 | | Reserved | 34h-3Bh | | WRITE VERIFY | 3Ch | | Reserved | 3Dh-3Fh | | READ VERIFY SECTOR(S) (w/retry) | 40 | | READ VERIFY SECTOR(S) (w/o retry) | 41 | | Reserved | 42h-4Fh | | FORMAT TRACK | 50h | | Reserved | 51h-5Fh | | Reserved | 60h-6Fh | | SEEK | 7xh | | Vendor unique | 8xh | | EXECUTE DRIVE DIAGNOSTIC | 90h | | INITIALIZE DRIVE PARAMETERS | 91h | | Download Microcode | 92h | | Reserved | 93h | | STANDBY IMMEDIATE | 94h E0h | | IDLE IMMEDIATE | 95h E1h | | STANDBY | 96h E2h | | IDLE | 97h E3h | | CHECK POWER MODE | 98h E5h | | SLEEP | 99h E6h | | Vendor unique | 9Ah | | Reserved | 9Bh-9Fh | | Reserved | A0h-AFh | | Reserved | B0h-BFh | | Vendor unique | C0-C3h | +------------------------------------+--------------+ Some commands have two command codes and appear in this table twice, once for each command code. Table 19 - Commands Sorted By Command Value (Part 1 of 2) +------------------------------------+--------------+ | Command Name | Command Code | +------------------------------------+--------------+ | READ MULTIPLE | C4h | | WRITE MULTIPLE | C5h | | SET MULTIPLE MODE | C6h | | Reserved | C7h | | READ DMA (w/retry) | C8h | | READ DMA (w/o retry) | C9h | | WRITE DMA (w/retry) | CAh | | WRITE DMA (w/o retry) | CBh | | Reserved | CCh-CFh | | Reserved | D0h-DAh | | ACKNOWLEDGE MEDIA CHANGE | DBh | | BOOT - POST-BOOT | DCh | | BOOT - PRE-BOOT | DDh | | DOOR LOCK | DEh | | DOOR UNLOCK | DFh | | STANDBY IMMEDIATE | 94h E0h | | IDLE IMMEDIATE | 95h E1h | | STANDBY | 96h E2h | | IDLE | 97h E3h | | READ BUFFER | E4h | | CHECK POWER MODE | 98h E5h | | SLEEP | 99h E6h | | Reserved | E7h | | WRITE BUFFER | E8h | | WRITE SAME | E9h | | Reserved | EAh-EBh | | IDENTIFY DRIVE | ECh | | Reserved | EDh-EEh | | SET FEATURES | EFh | | Vendor unique | F0h-FFh | +------------------------------------+--------------+ Some commands have two command codes and appear in this table twice, once for each command code. Table 19 - Commands Sorted By Command Value (Part 2 of 2) Annex F. IBM PC AT(tm) Bus Addresses (informative) The ATA bus contains two address select lines (CS0- and CS1-) which are the result of an address decode on the personal computer's main board or on an adapter board which is installed in the personal computer. The BIOS (Basic Input/Output System) and operating systems installed within these computers have established defacto standards for the I/O addresses used to address the ATA buses. While the number of ATA busses supported by a particular system implementation vary, the following table lists the addresses typically used. This information is provided for information only. There is no requirement that an implementation utilize these addresses. +------------+-------------+-------------+ | Bus Number | CS0- Decode | CS1- Decode | +------------+-------------+-------------+ | 1 | 01Fxh | 01Fxh | +------------+-------------+-------------+ | 2 | 00Fxh | 00Fxh | +------------+-------------+-------------+ | 3 | 017xh | 017xh | +------------+-------------+-------------+ | 4 | 007xh | 007xh | +------------+-------------+-------------+ X3T9.2/0948D Revision 0 X3T9.2/0948D Revision 0 Page 24 working draft AT Attachment Extensions working draft AT Attachment Extensions Page 25